]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
pinctrl: sunxi: add Allwinner D1 pinctrl description
authorAndre Przywara <andre.przywara@arm.com>
Mon, 5 Sep 2022 15:25:57 +0000 (16:25 +0100)
committerAndre Przywara <andre.przywara@arm.com>
Sun, 22 Oct 2023 22:41:51 +0000 (23:41 +0100)
Apart from using the new pinctrl MMIO register layout, the Allwinner D1
and related SoCs still need to usual set of mux values hardcoded in
U-Boot's pinctrl driver.
Add the values we need so far to this list, so that DM based drivers
will just work without further ado.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
drivers/pinctrl/sunxi/Kconfig
drivers/pinctrl/sunxi/pinctrl-sunxi.c

index 77da90836b6be2177658ff20edb3522bf2e08405..c8f937d91e99e6c88cdbe8a9cf122fcd90c07477 100644 (file)
@@ -124,4 +124,8 @@ config PINCTRL_SUN50I_H616_R
        default MACH_SUN50I_H616
        select PINCTRL_SUNXI
 
+config PINCTRL_SUN20I_D1
+       bool "Support for the Allwinner D1/R528 PIO"
+       select PINCTRL_SUNXI
+
 endif
index fc80fe50b1425f3586de8e140d42cff17594b9f9..bdf6360f176449f8edd5c35bbae633990d20d0b9 100644 (file)
@@ -598,6 +598,32 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_r_pinctrl_desc =
        .num_banks      = 3,
 };
 
+static const struct sunxi_pinctrl_function sun20i_d1_pinctrl_functions[] = {
+       { "emac",       8 },    /* PE0-PE15 */
+       { "gpio_in",    0 },
+       { "gpio_out",   1 },
+       { "i2c0",       4 },    /* PB10-PB11 */
+       { "mmc0",       2 },    /* PF0-PF5 */
+       { "mmc1",       2 },    /* PG0-PG5 */
+       { "mmc2",       3 },    /* PC2-PC7 */
+       { "spi0",       2 },    /* PC2-PC7 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+       { "uart0",      3 },    /* PF2,PF4 */
+#else
+       { "uart0",      6 },    /* PB0-PB1, PB8-PB9, PE2-PE3 */
+#endif
+       { "uart1",      2 },    /* PG6-PG7 */
+       { "uart2",      7 },    /* PB0-PB1 */
+       { "uart3",      7 },    /* PB6-PB7 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun20i_d1_pinctrl_desc = {
+       .functions      = sun20i_d1_pinctrl_functions,
+       .num_functions  = ARRAY_SIZE(sun20i_d1_pinctrl_functions),
+       .first_bank     = SUNXI_GPIO_A,
+       .num_banks      = 7,
+};
+
 static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
        { "emac",       4 },    /* PD8-PD23 */
        { "gpio_in",    0 },
@@ -863,6 +889,12 @@ static const struct udevice_id sunxi_pinctrl_ids[] = {
                .data = (ulong)&sun9i_a80_r_pinctrl_desc,
        },
 #endif
+#ifdef CONFIG_PINCTRL_SUN20I_D1
+       {
+               .compatible = "allwinner,sun20i-d1-pinctrl",
+               .data = (ulong)&sun20i_d1_pinctrl_desc,
+       },
+#endif
 #ifdef CONFIG_PINCTRL_SUN50I_A64
        {
                .compatible = "allwinner,sun50i-a64-pinctrl",