struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
unsigned int val, cache_id;
-
/*
* Must disable the L2 before changing the latency parameters
* and auxiliary control register.
board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
&phys_sdram_2_start, &phys_sdram_2_size);
-
end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
for (mr = 0; mr < 64; mr++) {
err = get_owned_memreg(mr, &start, &end);
board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
&phys_sdram_2_start, &phys_sdram_2_size);
-
end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;
return rate;
}
-
static enum scg_clk scg_scs_array[4] = {
SCG_SOSC_CLK, SCG_SIRC_CLK, SCG_FIRC_CLK, SCG_ROSC_CLK,
};
return 0;
}
-
/* A7 domain system clock source is SPLL */
#define SCG1_RCCR_SCS_NUM ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT)