clocks: qcom: Add clock driver for QCS404 SoC

Currently this clock driver initializes clocks for UART and eMMC. Along
with this import "qcom,gcc-qcs404.h" header from Linux mainline to
support DT bindings.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

diff --git a/arch/arm/mach-snapdragon/clock-qcs404.c b/arch/arm/mach-snapdragon/clock-qcs404.c
new file mode 100644 (file)
index 0000000..bb8a6fe
--- /dev/null
+++ b/arch/arm/mach-snapdragon/clock-qcs404.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Clock drivers for Qualcomm QCS404
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include "clock-snapdragon.h"
+
+#include <dt-bindings/clock/qcom,gcc-qcs404.h>
+
+/* GPLL0 clock control registers */
+#define GPLL0_STATUS_ACTIVE BIT(31)
+
+static struct vote_clk gcc_blsp1_ahb_clk = {
+       .cbcr_reg = BLSP1_AHB_CBCR,
+       .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
+       .vote_bit = BIT(10) | BIT(5) | BIT(4),
+};
+
+static const struct bcr_regs uart2_regs = {
+       .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
+       .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
+       .M = BLSP1_UART2_APPS_M,
+       .N = BLSP1_UART2_APPS_N,
+       .D = BLSP1_UART2_APPS_D,
+};
+
+static const struct bcr_regs sdc_regs = {
+       .cfg_rcgr = SDCC_CFG_RCGR(1),
+       .cmd_rcgr = SDCC_CMD_RCGR(1),
+       .M = SDCC_M(1),
+       .N = SDCC_N(1),
+       .D = SDCC_D(1),
+};
+
+static struct pll_vote_clk gpll0_vote_clk = {
+       .status = GPLL0_STATUS,
+       .status_bit = GPLL0_STATUS_ACTIVE,
+       .ena_vote = APCS_GPLL_ENA_VOTE,
+       .vote_bit = BIT(0),
+};
+
+ulong msm_set_rate(struct clk *clk, ulong rate)
+{
+       struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+       switch (clk->id) {
+       case GCC_BLSP1_UART2_APPS_CLK:
+               /* UART: 115200 */
+               clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
+                                    CFG_CLK_SRC_CXO);
+               clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
+               break;
+       case GCC_BLSP1_AHB_CLK:
+               clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
+               break;
+       case GCC_SDCC1_APPS_CLK:
+               /* SDCC1: 200MHz */
+               clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 4, 0, 0,
+                                    CFG_CLK_SRC_GPLL0);
+               clk_enable_gpll0(priv->base, &gpll0_vote_clk);
+               clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
+               break;
+       case GCC_SDCC1_AHB_CLK:
+               clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
+               break;
+       default:
+               return 0;
+       }
+
+       return 0;
+}

diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c
index 3deb08ac4a908edf6447bbf8f19fa93fbd12d9fb..5652d2fa36ec2802d4db15ab276e46b4b44db92e 100644 (file)
--- a/arch/arm/mach-snapdragon/clock-snapdragon.c
+++ b/arch/arm/mach-snapdragon/clock-snapdragon.c
@@ -136,6 +136,7 @@ static const struct udevice_id msm_clk_ids[] = {
        { .compatible = "qcom,gcc-msm8996" },
        { .compatible = "qcom,gcc-apq8096" },
        { .compatible = "qcom,gcc-sdm845" },
+       { .compatible = "qcom,gcc-qcs404" },
        { }
 };
 

diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h
new file mode 100644 (file)
index 0000000..4dc96b9
--- /dev/null
+++ b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Qualcomm QCS404 sysmap
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+#ifndef _MACH_SYSMAP_QCS404_H
+#define _MACH_SYSMAP_QCS404_H
+
+#define GICD_BASE                      (0x0b000000)
+#define GICC_BASE                      (0x0b002000)
+
+/* Clocks: (from CLK_CTL_BASE)  */
+#define GPLL0_STATUS                   (0x21000)
+#define APCS_GPLL_ENA_VOTE             (0x45000)
+#define APCS_CLOCK_BRANCH_ENA_VOTE     (0x45004)
+
+/* BLSP1 AHB clock (root clock for BLSP) */
+#define BLSP1_AHB_CBCR                 0x1008
+
+/* Uart clock control registers */
+#define BLSP1_UART2_BCR                        (0x3028)
+#define BLSP1_UART2_APPS_CBCR          (0x302C)
+#define BLSP1_UART2_APPS_CMD_RCGR      (0x3034)
+#define BLSP1_UART2_APPS_CFG_RCGR      (0x3038)
+#define BLSP1_UART2_APPS_M             (0x303C)
+#define BLSP1_UART2_APPS_N             (0x3040)
+#define BLSP1_UART2_APPS_D             (0x3044)
+
+/* SD controller clock control registers */
+#define SDCC_BCR(n)                    (((n) * 0x1000) + 0x41000)
+#define SDCC_CMD_RCGR(n)               (((n) * 0x1000) + 0x41004)
+#define SDCC_CFG_RCGR(n)               (((n) * 0x1000) + 0x41008)
+#define SDCC_M(n)                      (((n) * 0x1000) + 0x4100C)
+#define SDCC_N(n)                      (((n) * 0x1000) + 0x41010)
+#define SDCC_D(n)                      (((n) * 0x1000) + 0x41014)
+#define SDCC_APPS_CBCR(n)              (((n) * 0x1000) + 0x41018)
+#define SDCC_AHB_CBCR(n)               (((n) * 0x1000) + 0x4101C)
+
+#endif

diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
new file mode 100644 (file)
index 0000000..bc30515
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
@@ -0,0 +1,180 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
+
+#define GCC_APSS_AHB_CLK_SRC                           0
+#define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC                        1
+#define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC                        2
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC                        3
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC                        4
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC                        5
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC                        6
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC                        7
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC                        8
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC                        9
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC                        10
+#define GCC_BLSP1_UART0_APPS_CLK_SRC                   11
+#define GCC_BLSP1_UART1_APPS_CLK_SRC                   12
+#define GCC_BLSP1_UART2_APPS_CLK_SRC                   13
+#define GCC_BLSP1_UART3_APPS_CLK_SRC                   14
+#define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC                        15
+#define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC                        16
+#define GCC_BLSP2_UART0_APPS_CLK_SRC                   17
+#define GCC_BYTE0_CLK_SRC                              18
+#define GCC_EMAC_CLK_SRC                               19
+#define GCC_EMAC_PTP_CLK_SRC                           20
+#define GCC_ESC0_CLK_SRC                               21
+#define GCC_APSS_AHB_CLK                               22
+#define GCC_APSS_AXI_CLK                               23
+#define GCC_BIMC_APSS_AXI_CLK                          24
+#define GCC_BIMC_GFX_CLK                               25
+#define GCC_BIMC_MDSS_CLK                              26
+#define GCC_BLSP1_AHB_CLK                              27
+#define GCC_BLSP1_QUP0_I2C_APPS_CLK                    28
+#define GCC_BLSP1_QUP0_SPI_APPS_CLK                    29
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK                    30
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK                    31
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK                    32
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK                    33
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK                    34
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK                    35
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK                    36
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK                    37
+#define GCC_BLSP1_UART0_APPS_CLK                       38
+#define GCC_BLSP1_UART1_APPS_CLK                       39
+#define GCC_BLSP1_UART2_APPS_CLK                       40
+#define GCC_BLSP1_UART3_APPS_CLK                       41
+#define GCC_BLSP2_AHB_CLK                              42
+#define GCC_BLSP2_QUP0_I2C_APPS_CLK                    43
+#define GCC_BLSP2_QUP0_SPI_APPS_CLK                    44
+#define GCC_BLSP2_UART0_APPS_CLK                       45
+#define GCC_BOOT_ROM_AHB_CLK                           46
+#define GCC_DCC_CLK                                    47
+#define GCC_GENI_IR_H_CLK                              48
+#define GCC_ETH_AXI_CLK                                        49
+#define GCC_ETH_PTP_CLK                                        50
+#define GCC_ETH_RGMII_CLK                              51
+#define GCC_ETH_SLAVE_AHB_CLK                          52
+#define GCC_GENI_IR_S_CLK                              53
+#define GCC_GP1_CLK                                    54
+#define GCC_GP2_CLK                                    55
+#define GCC_GP3_CLK                                    56
+#define GCC_MDSS_AHB_CLK                               57
+#define GCC_MDSS_AXI_CLK                               58
+#define GCC_MDSS_BYTE0_CLK                             59
+#define GCC_MDSS_ESC0_CLK                              60
+#define GCC_MDSS_HDMI_APP_CLK                          61
+#define GCC_MDSS_HDMI_PCLK_CLK                         62
+#define GCC_MDSS_MDP_CLK                               63
+#define GCC_MDSS_PCLK0_CLK                             64
+#define GCC_MDSS_VSYNC_CLK                             65
+#define GCC_OXILI_AHB_CLK                              66
+#define GCC_OXILI_GFX3D_CLK                            67
+#define GCC_PCIE_0_AUX_CLK                             68
+#define GCC_PCIE_0_CFG_AHB_CLK                         69
+#define GCC_PCIE_0_MSTR_AXI_CLK                                70
+#define GCC_PCIE_0_PIPE_CLK                            71
+#define GCC_PCIE_0_SLV_AXI_CLK                         72
+#define GCC_PCNOC_USB2_CLK                             73
+#define GCC_PCNOC_USB3_CLK                             74
+#define GCC_PDM2_CLK                                   75
+#define GCC_PDM_AHB_CLK                                        76
+#define GCC_VSYNC_CLK_SRC                              77
+#define GCC_PRNG_AHB_CLK                               78
+#define GCC_PWM0_XO512_CLK                             79
+#define GCC_PWM1_XO512_CLK                             80
+#define GCC_PWM2_XO512_CLK                             81
+#define GCC_SDCC1_AHB_CLK                              82
+#define GCC_SDCC1_APPS_CLK                             83
+#define GCC_SDCC1_ICE_CORE_CLK                         84
+#define GCC_SDCC2_AHB_CLK                              85
+#define GCC_SDCC2_APPS_CLK                             86
+#define GCC_SYS_NOC_USB3_CLK                           87
+#define GCC_USB20_MOCK_UTMI_CLK                                88
+#define GCC_USB2A_PHY_SLEEP_CLK                                89
+#define GCC_USB30_MASTER_CLK                           90
+#define GCC_USB30_MOCK_UTMI_CLK                                91
+#define GCC_USB30_SLEEP_CLK                            92
+#define GCC_USB3_PHY_AUX_CLK                           93
+#define GCC_USB3_PHY_PIPE_CLK                          94
+#define GCC_USB_HS_PHY_CFG_AHB_CLK                     95
+#define GCC_USB_HS_SYSTEM_CLK                          96
+#define GCC_GFX3D_CLK_SRC                              97
+#define GCC_GP1_CLK_SRC                                        98
+#define GCC_GP2_CLK_SRC                                        99
+#define GCC_GP3_CLK_SRC                                        100
+#define GCC_GPLL0_OUT_MAIN                             101
+#define GCC_GPLL1_OUT_MAIN                             102
+#define GCC_GPLL3_OUT_MAIN                             103
+#define GCC_GPLL4_OUT_MAIN                             104
+#define GCC_HDMI_APP_CLK_SRC                           105
+#define GCC_HDMI_PCLK_CLK_SRC                          106
+#define GCC_MDP_CLK_SRC                                        107
+#define GCC_PCIE_0_AUX_CLK_SRC                         108
+#define GCC_PCIE_0_PIPE_CLK_SRC                                109
+#define GCC_PCLK0_CLK_SRC                              110
+#define GCC_PDM2_CLK_SRC                               111
+#define GCC_SDCC1_APPS_CLK_SRC                         112
+#define GCC_SDCC1_ICE_CORE_CLK_SRC                     113
+#define GCC_SDCC2_APPS_CLK_SRC                         114
+#define GCC_USB20_MOCK_UTMI_CLK_SRC                    115
+#define GCC_USB30_MASTER_CLK_SRC                       116
+#define GCC_USB30_MOCK_UTMI_CLK_SRC                    117
+#define GCC_USB3_PHY_AUX_CLK_SRC                       118
+#define GCC_USB_HS_SYSTEM_CLK_SRC                      119
+#define GCC_GPLL0_AO_CLK_SRC                           120
+#define GCC_USB_HS_INACTIVITY_TIMERS_CLK               122
+#define GCC_GPLL0_AO_OUT_MAIN                          123
+#define GCC_GPLL0_SLEEP_CLK_SRC                                124
+#define GCC_GPLL6                                      125
+#define GCC_GPLL6_OUT_AUX                              126
+#define GCC_MDSS_MDP_VOTE_CLK                          127
+#define GCC_MDSS_ROTATOR_VOTE_CLK                      128
+#define GCC_BIMC_GPU_CLK                               129
+#define GCC_GTCU_AHB_CLK                               130
+#define GCC_GFX_TCU_CLK                                        131
+#define GCC_GFX_TBU_CLK                                        132
+#define GCC_SMMU_CFG_CLK                               133
+#define GCC_APSS_TCU_CLK                               134
+#define GCC_CRYPTO_AHB_CLK                             135
+#define GCC_CRYPTO_AXI_CLK                             136
+#define GCC_CRYPTO_CLK                                 137
+#define GCC_MDP_TBU_CLK                                        138
+#define GCC_QDSS_DAP_CLK                               139
+#define GCC_DCC_XO_CLK                                 140
+#define GCC_WCSS_Q6_AHB_CLK                            141
+#define GCC_WCSS_Q6_AXIM_CLK                           142
+#define GCC_CDSP_CFG_AHB_CLK                           143
+#define GCC_BIMC_CDSP_CLK                              144
+#define GCC_CDSP_TBU_CLK                               145
+#define GCC_CDSP_BIMC_CLK_SRC                          146
+
+#define GCC_GENI_IR_BCR                                        0
+#define GCC_USB_HS_BCR                                 1
+#define GCC_USB2_HS_PHY_ONLY_BCR                       2
+#define GCC_QUSB2_PHY_BCR                              3
+#define GCC_USB_HS_PHY_CFG_AHB_BCR                     4
+#define GCC_USB2A_PHY_BCR                              5
+#define GCC_USB3_PHY_BCR                               6
+#define GCC_USB_30_BCR                                 7
+#define GCC_USB3PHY_PHY_BCR                            8
+#define GCC_PCIE_0_BCR                                 9
+#define GCC_PCIE_0_PHY_BCR                             10
+#define GCC_PCIE_0_LINK_DOWN_BCR                       11
+#define GCC_PCIEPHY_0_PHY_BCR                          12
+#define GCC_EMAC_BCR                                   13
+#define GCC_CDSP_RESTART                               14
+#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES              15
+#define GCC_PCIE_0_AHB_ARES                            16
+#define GCC_PCIE_0_AXI_SLAVE_ARES                      17
+#define GCC_PCIE_0_AXI_MASTER_ARES                     18
+#define GCC_PCIE_0_CORE_STICKY_ARES                    19
+#define GCC_PCIE_0_SLEEP_ARES                          20
+#define GCC_PCIE_0_PIPE_ARES                           21
+#define GCC_WDSP_RESTART                               22
+
+#endif