]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
spi: versal2: Enable spi drivers for Versal Gen 2
authorMichal Simek <michal.simek@amd.com>
Wed, 29 May 2024 14:48:01 +0000 (16:48 +0200)
committerMichal Simek <michal.simek@amd.com>
Mon, 17 Jun 2024 14:02:29 +0000 (16:02 +0200)
Enable and update OSPI/QSPI/GQSPI drivers to support Versal Gen 2 SoCs.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/691782470f56f7d49a3204f6757296f2752d4156.1716994063.git.michal.simek@amd.com
configs/amd_versal2_virt_defconfig
drivers/spi/Kconfig
drivers/spi/cadence_qspi.c
drivers/spi/zynqmp_gqspi.c

index b74e69be28c4065eb10c3431b4b735fa05f055a0..6e4adddf2c026ceafae62e2169044146cd1fa293 100644 (file)
@@ -5,7 +5,6 @@ CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864
 CONFIG_ARCH_VERSAL2=y
 CONFIG_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x100000
-CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-virt"
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
@@ -124,7 +123,10 @@ CONFIG_SOC_DEVICE=y
 CONFIG_SOC_AMD_VERSAL2=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_CADENCE_OSPI_VERSAL=y
 CONFIG_ZYNQ_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
 CONFIG_TPM2_TIS_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB_GADGET=y
index 35030ab3556101207e4230f9e1b2586930acbf21..cd785aefd56e8625dd21c76c59efc5edc9e6ba8a 100644 (file)
@@ -156,7 +156,7 @@ config CQSPI_REF_CLK
 
 config CADENCE_OSPI_VERSAL
        bool "Configure Versal OSPI"
-       depends on (ARCH_VERSAL || ARCH_VERSAL_NET) && CADENCE_QSPI
+       depends on (ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2) && CADENCE_QSPI
        imply DM_GPIO
        help
          This option is used to enable Versal OSPI DMA operations which
index 75e522320101a34352e06ad9c18e49b23ca353c3..9c466f8695e2b294e363d3112649d8ed1ef12ed3 100644 (file)
@@ -253,7 +253,8 @@ static int cadence_spi_probe(struct udevice *bus)
 
        /* Versal and Versal-NET use spi calibration to set read delay */
        if (CONFIG_IS_ENABLED(ARCH_VERSAL) ||
-           CONFIG_IS_ENABLED(ARCH_VERSAL_NET))
+           CONFIG_IS_ENABLED(ARCH_VERSAL_NET) ||
+           CONFIG_IS_ENABLED(ARCH_VERSAL2))
                if (priv->read_delay >= 0)
                        priv->read_delay = -1;
 
index 61349a4da53f708cec163186eaf839cde98a5aed..ae795e50b0a53efb4173d007efabb42ad6cb22bd 100644 (file)
 #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT  2
 #define GQSPI_DATA_DLY_ADJ_OFST                0x000001F8
 #define IOU_TAPDLY_BYPASS_OFST !(IS_ENABLED(CONFIG_ARCH_VERSAL) || \
-                                IS_ENABLED(CONFIG_ARCH_VERSAL_NET)) ? \
+                                IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || \
+                                IS_ENABLED(CONFIG_ARCH_VERSAL2)) ? \
                                0xFF180390 : 0xF103003C
 #define GQSPI_LPBK_DLY_ADJ_LPBK_MASK   0x00000020
 #define GQSPI_FREQ_37_5MHZ             37500000
@@ -316,7 +317,8 @@ static void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
                  __func__, clk_rate, baudrateval, reqhz);
 
        if (!(IS_ENABLED(CONFIG_ARCH_VERSAL) ||
-             IS_ENABLED(CONFIG_ARCH_VERSAL_NET))) {
+             IS_ENABLED(CONFIG_ARCH_VERSAL_NET) ||
+             IS_ENABLED(CONFIG_ARCH_VERSAL2))) {
                if (reqhz <= GQSPI_FREQ_40MHZ) {
                        tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
                                        TAP_DLY_BYPASS_LQSPI_RX_SHIFT;