ARM: tegra: amend pmc.h for Tegra114+

Tegra114 and later's PMC module removes the pwrgate_timer_on register
and replaces it with a clamp_status register. Adjust pmc.h to reflect
this, and update any code affected by the change.

The cpu.c change in this patch was extracted from a much larger patch
by Jimmy Zhang. The pmc.h change was written from scratch, but inspired
by related changes made by Tom Warren.

There could well be other differences in the PMC register set for chips
after Tegra20/30. However, they don't affect the code in U-Boot at
present, so I haven't attempted an exhaustive update of pmc.h.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c
index 51ecff794fb7f1cf85983a91ff671fd937a63e32..7a1747a3beb838b0909e1ec827a692c529136a0e 100644 (file)
--- a/arch/arm/cpu/arm720t/tegra114/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra114/cpu.c
@@ -219,8 +219,8 @@ static int is_clamp_enabled(u32 mask)
        struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
        u32 reg;
 
-       /* Get clamp status. TODO: Add pmc_clamp_status alias to pmc.h */
-       reg = readl(&pmc->pmc_pwrgate_timer_on);
+       /* Get clamp status. */
+       reg = readl(&pmc->pmc_clamp_status);
        return (reg & mask) == mask;
 }
 

diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h
index ba22236ee3b79b25036f12f0bd2f57df40da3d78..6e5f61e7fa4cec873473a42414eab60f0fc9ec85 100644 (file)
--- a/arch/arm/include/asm/arch-tegra/pmc.h
+++ b/arch/arm/include/asm/arch-tegra/pmc.h
@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2010,2011
+ *  (C) Copyright 2010,2011,2014
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:    GPL-2.0+
@@ -21,7 +21,11 @@ struct pmc_ctlr {
        uint pmc_dpd_sample;            /* _DPD_PADS_SAMPLE_0, offset 20 */
        uint pmc_dpd_enable;            /* _DPD_PADS_ENABLE_0, offset 24 */
        uint pmc_pwrgate_timer_off;     /* _PWRGATE_TIMER_OFF_0, offset 28 */
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
        uint pmc_pwrgate_timer_on;      /* _PWRGATE_TIMER_ON_0, offset 2C */
+#else
+       uint pmc_clamp_status;          /* _CLAMP_STATUS_0, offset 2C */
+#endif
        uint pmc_pwrgate_toggle;        /* _PWRGATE_TOGGLE_0, offset 30 */
        uint pmc_remove_clamping;       /* _REMOVE_CLAMPING_CMD_0, offset 34 */
        uint pmc_pwrgate_status;        /* _PWRGATE_STATUS_0, offset 38 */