riscv: add functions for reading the IPI status

Add the function riscv_get_ipi() for reading the pending status of IPIs.
The supported controllers are Andes' Platform Level Interrupt Controller
(PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local
Interruptor (CLINT).

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>

diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 42394b9b6e1e272a643d55c8cf042b36d22311f3..3868569a65a96d1ad4a7ad34901661d7ef87c0d0 100644 (file)
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -117,6 +117,17 @@ int riscv_clear_ipi(int hart)
        return 0;
 }
 
+int riscv_get_ipi(int hart, int *pending)
+{
+       PLIC_BASE_GET();
+
+       *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
+                                                    gd->arch.boot_hart));
+       *pending = !!(*pending & SEND_IPI_TO_HART(hart));
+
+       return 0;
+}
+
 static const struct udevice_id andes_plic_ids[] = {
        { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
        { }

diff --git a/arch/riscv/lib/sbi_ipi.c b/arch/riscv/lib/sbi_ipi.c
index 170346da68c23feca6c55506276720a3c386f795..9a698ce74e67127209c46cec82fbee9e2e907f19 100644 (file)
--- a/arch/riscv/lib/sbi_ipi.c
+++ b/arch/riscv/lib/sbi_ipi.c
@@ -23,3 +23,14 @@ int riscv_clear_ipi(int hart)
 
        return 0;
 }
+
+int riscv_get_ipi(int hart, int *pending)
+{
+       /*
+        * The SBI does not support reading the IPI status. We always return 0
+        * to indicate that no IPI is pending.
+        */
+       *pending = 0;
+
+       return 0;
+}

diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
index d24e0d585b5380b15102ba3f91cac6fcf89fa058..d7899d16d7a2be5fe988c450afa262d1eb99eb3d 100644 (file)
--- a/arch/riscv/lib/sifive_clint.c
+++ b/arch/riscv/lib/sifive_clint.c
@@ -71,6 +71,15 @@ int riscv_clear_ipi(int hart)
        return 0;
 }
 
+int riscv_get_ipi(int hart, int *pending)
+{
+       CLINT_BASE_GET();
+
+       *pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart));
+
+       return 0;
+}
+
 static const struct udevice_id sifive_clint_ids[] = {
        { .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT },
        { }

diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index 705437862a0d1402f13c4cf0f5e62e6ccabb5d06..188a7e34bd071128b1de31041b090dc030880bf8 100644 (file)
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -32,6 +32,18 @@ extern int riscv_send_ipi(int hart);
  */
 extern int riscv_clear_ipi(int hart);
 
+/**
+ * riscv_get_ipi() - Get status of inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of hart to be checked
+ * @pending: Pointer to variable with result of the check,
+ *           1 if IPI is pending, 0 otherwise
+ * @return 0 if OK, -ve on error
+ */
+extern int riscv_get_ipi(int hart, int *pending);
+
 static int send_ipi_many(struct ipi_data *ipi)
 {
        ofnode node, cpus;