pci: mvebu: Fix Armada 38x support

Armada 38x has four PCI ports, not three.

The optimization in pci_init_board() seems to assume that every port has
three lanes. This is obviously wrong, and breaks support for Armada 38x.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index 0f69f3341be013852dc625ef7d6bd48eb3c0ce9c..0900e4008c12ec3489c0b5357c43ada791cce711 100644 (file)
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -67,6 +67,7 @@
 #define MVEBU_REG_PCIE_BASE    (MVEBU_REGISTER(0x40000))
 #define MVEBU_AXP_USB_BASE      (MVEBU_REGISTER(0x50000))
 #define MVEBU_USB20_BASE       (MVEBU_REGISTER(0x58000))
+#define MVEBU_REG_PCIE0_BASE   (MVEBU_REGISTER(0x80000))
 #define MVEBU_AXP_SATA_BASE    (MVEBU_REGISTER(0xa0000))
 #define MVEBU_SATA0_BASE       (MVEBU_REGISTER(0xa8000))
 #define MVEBU_NAND_BASE                (MVEBU_REGISTER(0xd0000))

diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index 0f449703de72dabb9f9437d8da9ec180eb00c212..da0aa29865e921ca7b2240445b016dafcb3a635c 100644 (file)
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -91,25 +91,26 @@ static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE;
 #if defined(CONFIG_ARMADA_38X)
 #define PCIE_BASE(if)                                  \
        ((if) == 0 ?                                    \
-        MVEBU_REG_PCIE_BASE + 0x40000 :                \
-        MVEBU_REG_PCIE_BASE + 0x4000 * (if))
+        MVEBU_REG_PCIE0_BASE :                         \
+        (MVEBU_REG_PCIE_BASE + 0x4000 * (if - 1)))
 
 /*
  * On A38x MV6820 these PEX ports are supported:
  *  0 - Port 0.0
- *  1 - Port 0.1
- *  2 - Port 0.2
+ *  1 - Port 1.0
+ *  2 - Port 2.0
+ *  3 - Port 3.0
  */
-#define MAX_PEX 3
+#define MAX_PEX 4
 static struct mvebu_pcie pcie_bus[MAX_PEX];
 
 static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx,
                                int *mem_target, int *mem_attr)
 {
-       u8 port[] = { 0, 1, 2 };
-       u8 lane[] = { 0, 0, 0 };
-       u8 target[] = { 8, 4, 4 };
-       u8 attr[] = { 0xe8, 0xe8, 0xd8 };
+       u8 port[] = { 0, 1, 2, 3 };
+       u8 lane[] = { 0, 0, 0, 0 };
+       u8 target[] = { 8, 4, 4, 4 };
+       u8 attr[] = { 0xe8, 0xe8, 0xd8, 0xb8 };
 
        pcie->port = port[pex_idx];
        pcie->lane = lane[pex_idx];
@@ -351,9 +352,9 @@ void pci_init_board(void)
                mvebu_get_port_lane(pcie, i, &mem_target, &mem_attr);
 
                /* Don't read at all from pci registers if port power is down */
-               if (pcie->lane == 0 && SELECT(soc_ctrl, pcie->port) == 0) {
-                       i += 3;
-                       debug("%s: skipping port %d\n", __func__, pcie->port);
+               if (SELECT(soc_ctrl, pcie->port) == 0) {
+                       if (pcie->lane == 0)
+                               debug("%s: skipping port %d\n", __func__, pcie->port);
                        continue;
                }