clk: sunxi: Implement UART resets

Implement UART resets for all relevant Allwinner SoC
clock drivers via ccu reset table.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>

diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
index ebe8d0002c342c7b8ad465eaacd8c2e0e26fc891..854259bf816d2cf42d450e3b0d04a813804381a5 100644 (file)
--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -38,6 +38,12 @@ static struct ccu_reset a23_resets[] = {
        [RST_BUS_OTG]           = RESET(0x2c0, BIT(24)),
        [RST_BUS_EHCI]          = RESET(0x2c0, BIT(26)),
        [RST_BUS_OHCI]          = RESET(0x2c0, BIT(29)),
+
+       [RST_BUS_UART0]         = RESET(0x2d8, BIT(16)),
+       [RST_BUS_UART1]         = RESET(0x2d8, BIT(17)),
+       [RST_BUS_UART2]         = RESET(0x2d8, BIT(18)),
+       [RST_BUS_UART3]         = RESET(0x2d8, BIT(19)),
+       [RST_BUS_UART4]         = RESET(0x2d8, BIT(20)),
 };
 
 static const struct ccu_desc a23_ccu_desc = {

diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index 145df5c19fb0d62a8ced7a6bc56c48ea0ff27f61..a38d76cb7c73d8ee1b6fd04cd6c96a5c79d4e1c9 100644 (file)
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -46,6 +46,13 @@ static struct ccu_reset a31_resets[] = {
        [RST_AHB1_OHCI0]        = RESET(0x2c0, BIT(29)),
        [RST_AHB1_OHCI1]        = RESET(0x2c0, BIT(30)),
        [RST_AHB1_OHCI2]        = RESET(0x2c0, BIT(31)),
+
+       [RST_APB2_UART0]        = RESET(0x2d8, BIT(16)),
+       [RST_APB2_UART1]        = RESET(0x2d8, BIT(17)),
+       [RST_APB2_UART2]        = RESET(0x2d8, BIT(18)),
+       [RST_APB2_UART3]        = RESET(0x2d8, BIT(19)),
+       [RST_APB2_UART4]        = RESET(0x2d8, BIT(20)),
+       [RST_APB2_UART5]        = RESET(0x2d8, BIT(21)),
 };
 
 static const struct ccu_desc a31_ccu_desc = {

diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 63424a9e2db872810f4f43af5adcc93eae358a06..a2ba6eefc57493332cc65e52f23d1586e0688741 100644 (file)
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -43,6 +43,12 @@ static const struct ccu_reset a64_resets[] = {
        [RST_BUS_EHCI1]         = RESET(0x2c0, BIT(25)),
        [RST_BUS_OHCI0]         = RESET(0x2c0, BIT(28)),
        [RST_BUS_OHCI1]         = RESET(0x2c0, BIT(29)),
+
+       [RST_BUS_UART0]         = RESET(0x2d8, BIT(16)),
+       [RST_BUS_UART1]         = RESET(0x2d8, BIT(17)),
+       [RST_BUS_UART2]         = RESET(0x2d8, BIT(18)),
+       [RST_BUS_UART3]         = RESET(0x2d8, BIT(19)),
+       [RST_BUS_UART4]         = RESET(0x2d8, BIT(20)),
 };
 
 static const struct ccu_desc a64_ccu_desc = {

diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index 76099fd15449c64aebfd0b533e3214296f88ddc5..1ef6ac5b25695a1d7702aa4c62077c33297e547e 100644 (file)
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -40,6 +40,12 @@ static struct ccu_reset a83t_resets[] = {
        [RST_BUS_EHCI0]         = RESET(0x2c0, BIT(26)),
        [RST_BUS_EHCI1]         = RESET(0x2c0, BIT(27)),
        [RST_BUS_OHCI0]         = RESET(0x2c0, BIT(29)),
+
+       [RST_BUS_UART0]         = RESET(0x2d8, BIT(16)),
+       [RST_BUS_UART1]         = RESET(0x2d8, BIT(17)),
+       [RST_BUS_UART2]         = RESET(0x2d8, BIT(18)),
+       [RST_BUS_UART3]         = RESET(0x2d8, BIT(19)),
+       [RST_BUS_UART4]         = RESET(0x2d8, BIT(20)),
 };
 
 static const struct ccu_desc a83t_ccu_desc = {

diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index 69c2aa34a3d2e11d842398e6ba34f3250fa1cb10..f82949b3b65cb109012ff237ac37cf66966ed112 100644 (file)
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -53,6 +53,11 @@ static struct ccu_reset h3_resets[] = {
        [RST_BUS_OHCI1]         = RESET(0x2c0, BIT(29)),
        [RST_BUS_OHCI2]         = RESET(0x2c0, BIT(30)),
        [RST_BUS_OHCI3]         = RESET(0x2c0, BIT(31)),
+
+       [RST_BUS_UART0]         = RESET(0x2d8, BIT(16)),
+       [RST_BUS_UART1]         = RESET(0x2d8, BIT(17)),
+       [RST_BUS_UART2]         = RESET(0x2d8, BIT(18)),
+       [RST_BUS_UART3]         = RESET(0x2d8, BIT(19)),
 };
 
 static const struct ccu_desc h3_ccu_desc = {

diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index 9a632b2603fc187b16f52a3241510c8cd93a7f2f..fd7aae97eada3bbdf51a16f07fa0643080f92c78 100644 (file)
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -50,6 +50,15 @@ static struct ccu_reset r40_resets[] = {
        [RST_BUS_OHCI0]         = RESET(0x2c0, BIT(29)),
        [RST_BUS_OHCI1]         = RESET(0x2c0, BIT(30)),
        [RST_BUS_OHCI2]         = RESET(0x2c0, BIT(31)),
+
+       [RST_BUS_UART0]         = RESET(0x2d8, BIT(16)),
+       [RST_BUS_UART1]         = RESET(0x2d8, BIT(17)),
+       [RST_BUS_UART2]         = RESET(0x2d8, BIT(18)),
+       [RST_BUS_UART3]         = RESET(0x2d8, BIT(19)),
+       [RST_BUS_UART4]         = RESET(0x2d8, BIT(20)),
+       [RST_BUS_UART5]         = RESET(0x2d8, BIT(21)),
+       [RST_BUS_UART6]         = RESET(0x2d8, BIT(22)),
+       [RST_BUS_UART7]         = RESET(0x2d8, BIT(23)),
 };
 
 static const struct ccu_desc r40_ccu_desc = {

diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index a268786b2d808acf3f71bbd253ac6209da3a7eeb..25ad87500e15d45124fa426f336274474c4f70aa 100644 (file)
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -26,6 +26,10 @@ static struct ccu_reset v3s_resets[] = {
        [RST_USB_PHY0]          = RESET(0x0cc, BIT(0)),
 
        [RST_BUS_OTG]           = RESET(0x2c0, BIT(24)),
+
+       [RST_BUS_UART0]         = RESET(0x2d8, BIT(16)),
+       [RST_BUS_UART1]         = RESET(0x2d8, BIT(17)),
+       [RST_BUS_UART2]         = RESET(0x2d8, BIT(18)),
 };
 
 static const struct ccu_desc v3s_ccu_desc = {