mips: bmips: add bcm63xx-hsspi driver support for BCM6328

This driver manages the SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>

diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi
index a99607574357bfd68a7cd0b5a9a537441defd3e2..67d9278be49b5d7fc8e73477b588a6b48a995955 100644 (file)
--- a/arch/mips/dts/brcm,bcm6328.dtsi
+++ b/arch/mips/dts/brcm,bcm6328.dtsi
@@ -13,6 +13,10 @@
 / {
        compatible = "brcm,bcm6328";
 
+       aliases {
+               spi0 = &spi;
+       };
+
        cpus {
                reg = <0x10000000 0x4>;
                #address-cells = <1>;
@@ -40,6 +44,12 @@
                #size-cells = <1>;
                u-boot,dm-pre-reloc;
 
+               hsspi_pll: hsspi-pll {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <133333333>;
+               };
+
                periph_osc: periph-osc {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
@@ -123,6 +133,20 @@
                        status = "disabled";
                };
 
+               spi: spi@10001000 {
+                       compatible = "brcm,bcm6328-hsspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x10001000 0x600>;
+                       clocks = <&periph_clk BCM6328_CLK_HSSPI>, <&hsspi_pll>;
+                       clock-names = "hsspi", "pll";
+                       resets = <&periph_rst BCM6328_RST_SPI>;
+                       spi-max-frequency = <33333334>;
+                       num-cs = <3>;
+
+                       status = "disabled";
+               };
+
                periph_pwr: power-controller@10001848 {
                        compatible = "brcm,bcm6328-power-domain";
                        reg = <0x10001848 0x4>;