x86: Avoid timer-clock overflow

When the clock speed is above about 4GHz, e.g. on modern PC hardware,
the timer overflows, resulting in a much lower frequency than expected.
Deal with this by capping the clock speed.

It would be possible to move to a 64-bit value for the clock, but that
is a pain to deal with. A better approach might be to express the clock
in MHz but that is left for later consideration.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index d11227cf440d3ecc9e798799106eed1b88604be1..2f2c2f27b7ff07af38c12d4780e9b486906baa09 100644 (file)
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -442,6 +442,7 @@ static void tsc_timer_ensure_setup(bool early)
                        return;
 
 done:
+               fast_calibrate = min(fast_calibrate, 4000UL);
                if (!gd->arch.clock_rate)
                        gd->arch.clock_rate = fast_calibrate * 1000000;
        }