spl: add support to booting with OP-TEE

OP-TEE is an open source trusted OS, in armv7, its loading and
running are like this:
loading:
- SPL load both OP-TEE and U-Boot
running:
- SPL run into OP-TEE in secure mode;
- OP-TEE run into U-Boot in non-secure mode;

To make code simple, it would be fine to use IH_OS_TEE for the
os tyle in TPL(just like IH_OS_LINUX is using both in SPL and U-Boot).

Here is the diagram for SPL loading OP-TEE,
IH_OS_TEE:(make u-boot.itb for SPL)
    Non-Secure       Secure

                     BootROM
                       |
                       v
                      SPL
                       |
                       v
          ---------  OP-TEE
         |
         v
       U-Boot
         |
         V
       Linux
For other two king of OP-TEE loading/booting, see commit message:
45b55712d4 image: Add IH_OS_TEE for TEE chain-load boot

More detail:
https://github.com/OP-TEE/optee_os
and search for 'boot arguments' for detail entry parameter in:
core/arch/arm/kernel/generic_entry_a32.S

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Cc: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 18dbc238bf6f3803c2a7c553c8523943514bc74e..d0564621d4ddd94a44fcdd9268dbcc2e556e3d02 100644 (file)
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -832,6 +832,13 @@ config SPL_AM33XX_ENABLE_RTC32K_OSC
          Enable access to the AM33xx RTC and select the external 32kHz clock
          source.
 
+config SPL_OPTEE
+       bool "Support OP-TEE Trusted OS"
+       depends on ARM
+       help
+         OP-TEE is an open source Trusted OS  which is loaded by SPL.
+         More detail at: https://github.com/OP-TEE/optee_os
+
 config TPL
        bool
        depends on SUPPORT_TPL

diff --git a/common/spl/Makefile b/common/spl/Makefile
index 814081fedab9c385573b5c5e541fe260aec2ca31..a130a5be4b0e6609981bea8ff1f0dc862bb0fb48 100644 (file)
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_$(SPL_TPL_)UBI) += spl_ubi.o
 obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o
 obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o
 obj-$(CONFIG_$(SPL_TPL_)ATF) += spl_atf.o
+obj-$(CONFIG_$(SPL_TPL_)OPTEE) += spl_optee.o
 obj-$(CONFIG_$(SPL_TPL_)USB_SUPPORT) += spl_usb.o
 obj-$(CONFIG_$(SPL_TPL_)FAT_SUPPORT) += spl_fat.o
 obj-$(CONFIG_$(SPL_TPL_)EXT_SUPPORT) += spl_ext.o

diff --git a/common/spl/spl.c b/common/spl/spl.c
index 038f2b0e83c328f28cf9e814950773c5c41cfc18..292e659c9ac4cad92e17c269c9205308a6be38c6 100644 (file)
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -536,6 +536,13 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
                spl_invoke_atf(&spl_image);
                break;
 #endif
+#if CONFIG_IS_ENABLED(OPTEE)
+       case IH_OS_TEE:
+               debug("Jumping to U-Boot via OP-TEE\n");
+               spl_optee_entry(NULL, NULL, spl_image.fdt_addr,
+                               (void *)spl_image.entry_point);
+               break;
+#endif
 #ifdef CONFIG_SPL_OS_BOOT
        case IH_OS_LINUX:
                debug("Jumping to Linux\n");

diff --git a/common/spl/spl_optee.S b/common/spl/spl_optee.S
new file mode 100644 (file)
index 0000000..86fc398
--- /dev/null
+++ b/common/spl/spl_optee.S
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Rockchip Electronic Co.,Ltd
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+ENTRY(spl_optee_entry)
+       ldr lr, =CONFIG_SYS_TEXT_BASE
+       mov pc, r3
+ENDPROC(spl_optee_entry)

diff --git a/include/spl.h b/include/spl.h
index b42683c9e71a99bcb41fe53a5198f98d59989011..9a439f468b9b0ad876b7e2677ccd1dd4467fcc2f 100644 (file)
--- a/include/spl.h
+++ b/include/spl.h
@@ -288,6 +288,19 @@ int spl_mmc_load_image(struct spl_image_info *spl_image,
  */
 void spl_invoke_atf(struct spl_image_info *spl_image);
 
+/**
+ * spl_optee_entry - entry function for optee
+ *
+ * args defind in op-tee project
+ * https://github.com/OP-TEE/optee_os/
+ * core/arch/arm/kernel/generic_entry_a32.S
+ * @arg0: pagestore
+ * @arg1: (ARMv7 standard bootarg #1)
+ * @arg2: device tree address, (ARMv7 standard bootarg #2)
+ * @arg3: non-secure entry address (ARMv7 bootarg #0)
+ */
+void spl_optee_entry(void *arg0, void *arg1, void *arg2, void *arg3);
+
 /**
  * board_return_to_bootrom - allow for boards to continue with the boot ROM
  *