socfpga: Creating driver for Reset Manager

Consolidating reset code into reset_manager.c. Also
separating reset configuration for virtual target and
real hardware Cyclone V development kit

Signed-off-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>

diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile
index 3b48ac9b2b275f9a6059a5f4e4c06bfedeb843ba..5024fc55e275d6f11e12830b3cdc5eea4b5704ef 100644 (file)
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -13,7 +13,7 @@ include $(TOPDIR)/config.mk
 LIB    =  $(obj)lib$(SOC).o
 
 SOBJS  := lowlevel_init.o
-COBJS-y        := misc.o timer.o
+COBJS-y        := misc.o timer.o reset_manager.o
 COBJS-$(CONFIG_SPL_BUILD) += spl.o
 
 COBJS  := $(COBJS-y)

diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
index 66edb3c20fbba6d20c9efbae32a6446e8c21be6d..2f1c7160f1ff458bef09c2a3b7078a540d47b5e8 100644 (file)
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -6,36 +6,9 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/reset_manager.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_reset_manager *reset_manager_base =
-               (void *)SOCFPGA_RSTMGR_ADDRESS;
-
-/*
- * Write the reset manager register to cause reset
- */
-void reset_cpu(ulong addr)
-{
-       /* request a warm reset */
-       writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl);
-       /*
-        * infinite loop here as watchdog will trigger and reset
-        * the processor
-        */
-       while (1)
-               ;
-}
-
-/*
- * Release peripherals from reset based on handoff
- */
-void reset_deassert_peripherals_handoff(void)
-{
-       writel(0, &reset_manager_base->per_mod_reset);
-}
-
 int dram_init(void)
 {
        gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);

diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c
new file mode 100644 (file)
index 0000000..e320c01
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -0,0 +1,39 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_reset_manager *reset_manager_base =
+               (void *)SOCFPGA_RSTMGR_ADDRESS;
+
+/*
+ * Write the reset manager register to cause reset
+ */
+void reset_cpu(ulong addr)
+{
+       /* request a warm reset */
+       writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
+               &reset_manager_base->ctrl);
+       /*
+        * infinite loop here as watchdog will trigger and reset
+        * the processor
+        */
+       while (1)
+               ;
+}
+
+/*
+ * Release peripherals from reset based on handoff
+ */
+void reset_deassert_peripherals_handoff(void)
+{
+       writel(0, &reset_manager_base->per_mod_reset);
+}

diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h
index 13d73577023d23c6f86e776026f1ac3067632950..3e9547682833c25cfd2e5c5c0c48f49c05a570ed 100644 (file)
--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -11,16 +11,20 @@ void reset_cpu(ulong addr);
 void reset_deassert_peripherals_handoff(void);
 
 struct socfpga_reset_manager {
-       u32     padding1;
+       u32     status;
        u32     ctrl;
-       u32     padding2;
-       u32     padding3;
+       u32     counts;
+       u32     padding1;
        u32     mpu_mod_reset;
        u32     per_mod_reset;
        u32     per2_mod_reset;
        u32     brg_mod_reset;
 };
 
+#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
+#else
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
+#endif
 
 #endif /* _RESET_MANAGER_H_ */