arm: socfpga: stratix10: Enable SMMU access

Enable TCU access through the Stratix10 CCU so that the
SMMU can access the SDRAM.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>

diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h
index 516bd1c0e1ec96eaa1d19ab0628a8062cf33b5ee..430341bea14c8fcdd6f865147706fb06ffae9c3d 100644 (file)
--- a/arch/arm/mach-socfpga/include/mach/firewall.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -95,6 +95,13 @@ struct socfpga_firwall_l4_sys {
 
 #define CCU_IOM_MPRT_ADMASK_MEM_RAM0           0x18628
 
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE0          0x2c520
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1A         0x2c540
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1B         0x2c560
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1C         0x2c580
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1D         0x2c5a0
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1E         0x2c5c0
+
 #define CCU_ADMASK_P_MASK                      BIT(0)
 #define CCU_ADMASK_NS_MASK                     BIT(1)
 

diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index b709758db7c40eee4edff3862d55460c3ec8a655..cf586ac860dc61ce25dc0f4322013b1983280d39 100644 (file)
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -105,6 +105,20 @@ int sdram_mmr_init_full(struct udevice *dev)
        clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E),
                     CCU_ADBASE_DI_MASK);
 
+       /* Enable access to DDR from TCU */
+       clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE0),
+                    CCU_ADBASE_DI_MASK);
+       clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1A),
+                    CCU_ADBASE_DI_MASK);
+       clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1B),
+                    CCU_ADBASE_DI_MASK);
+       clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1C),
+                    CCU_ADBASE_DI_MASK);
+       clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1D),
+                    CCU_ADBASE_DI_MASK);
+       clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1E),
+                    CCU_ADBASE_DI_MASK);
+
        /* this enables nonsecure access to DDR */
        /* mpuregion0addr_limit */
        FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);