mmc: versal2: Update zynq_sdhci driver to support AMD Versal Gen 2

Enable tap delay programming for new SoC and also enable it via defconfig.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f07daded9704cbc393657b65a28933c34a8cec25.1716994063.git.michal.simek@amd.com

diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig
index 8ef86f1f383052c9cf8cbd3b807d643da04a5d72..b74e69be28c4065eb10c3431b4b735fa05f055a0 100644 (file)
--- a/configs/amd_versal2_virt_defconfig
+++ b/configs/amd_versal2_virt_defconfig
@@ -87,6 +87,8 @@ CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y

diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 8a83adef43429ae6a91cd0c5bb0a3a7934a6b191..28d2b456fbf6e8001d121970d6613175843f4aff 100644 (file)
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -122,7 +122,8 @@ __weak int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
        return 1;
 }
 
-#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET)
+#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || \
+    defined(CONFIG_ARCH_VERSAL_NET) || defined(CONFIG_ARCH_VERSAL2)
 /* Default settings for ZynqMP Clock Phases */
 static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63,  0,
                                         0, 183, 54,  0, 0};
@@ -156,7 +157,7 @@ static const u8 mode2timing[] = {
        [MMC_HS_400] = MMC_TIMING_MMC_HS400,
 };
 
-#if defined(CONFIG_ARCH_VERSAL_NET)
+#if defined(CONFIG_ARCH_VERSAL_NET) || defined(CONFIG_ARCH_VERSAL2)
 /**
  * arasan_phy_set_delaychain - Set eMMC delay chain based Input/Output clock
  *
@@ -866,7 +867,8 @@ static int arasan_sdhci_set_tapdelay(struct sdhci_host *host)
                if (ret)
                        return ret;
        } else if ((IS_ENABLED(CONFIG_ARCH_VERSAL) ||
-                   IS_ENABLED(CONFIG_ARCH_VERSAL_NET)) &&
+                   IS_ENABLED(CONFIG_ARCH_VERSAL_NET) ||
+                   IS_ENABLED(CONFIG_ARCH_VERSAL2)) &&
                   device_is_compatible(dev, "xlnx,versal-8.9a")) {
                ret = sdhci_versal_sampleclk_set_phase(host, iclk_phase);
                if (ret)
@@ -875,7 +877,8 @@ static int arasan_sdhci_set_tapdelay(struct sdhci_host *host)
                ret = sdhci_versal_sdcardclk_set_phase(host, oclk_phase);
                if (ret)
                        return ret;
-       } else if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) &&
+       } else if ((IS_ENABLED(CONFIG_ARCH_VERSAL_NET) ||
+                   IS_ENABLED(CONFIG_ARCH_VERSAL2)) &&
                   device_is_compatible(dev, "xlnx,versal-net-emmc")) {
                if (mmc->clock >= MIN_PHY_CLK_HZ)
                        if (iclk_phase == VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN)
@@ -943,7 +946,8 @@ static void arasan_dt_parse_clk_phases(struct udevice *dev)
        }
 
        if ((IS_ENABLED(CONFIG_ARCH_VERSAL) ||
-            IS_ENABLED(CONFIG_ARCH_VERSAL_NET)) &&
+            IS_ENABLED(CONFIG_ARCH_VERSAL_NET) ||
+            IS_ENABLED(CONFIG_ARCH_VERSAL2)) &&
            device_is_compatible(dev, "xlnx,versal-8.9a")) {
                for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
                        clk_data->clk_phase_in[i] = versal_iclk_phases[i];
@@ -951,7 +955,8 @@ static void arasan_dt_parse_clk_phases(struct udevice *dev)
                }
        }
 
-       if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) &&
+       if ((IS_ENABLED(CONFIG_ARCH_VERSAL_NET) ||
+            IS_ENABLED(CONFIG_ARCH_VERSAL2)) &&
            device_is_compatible(dev, "xlnx,versal-net-emmc")) {
                for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
                        clk_data->clk_phase_in[i] = versal_net_emmc_iclk_phases[i];
@@ -987,7 +992,7 @@ static const struct sdhci_ops arasan_ops = {
        .platform_execute_tuning        = &arasan_sdhci_execute_tuning,
        .set_delay = &arasan_sdhci_set_tapdelay,
        .set_control_reg = &sdhci_set_control_reg,
-#if defined(CONFIG_ARCH_VERSAL_NET)
+#if defined(CONFIG_ARCH_VERSAL_NET) || defined(CONFIG_ARCH_VERSAL2)
        .config_dll = &arasan_sdhci_config_dll,
 #endif
 };
@@ -1195,7 +1200,8 @@ static int arasan_sdhci_of_to_plat(struct udevice *dev)
 
        priv->host->name = dev->name;
 
-#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET)
+#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET) || \
+    defined(CONFIG_ARCH_VERSAL2)
        priv->host->ops = &arasan_ops;
        arasan_dt_parse_clk_phases(dev);
 #endif