clk: starfive: pll: Fix to use postdiv1_mask

There is a problem that the rates of PLL0 and PLL1 are set incorrectly
because the postdiv1_mask value is incorrectly entered when setting
the pll clk reg. Modify postdiv1's mask value to be put correctly.

Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c
index 02e6d9000e292dfc71ab4e474abdea08baa7da20..7492b1f70dd4830948a2985f68cd92a492f4094e 100644 (file)
--- a/drivers/clk/starfive/clk-jh7110-pll.c
+++ b/drivers/clk/starfive/clk-jh7110-pll.c
@@ -185,7 +185,7 @@ static void jh7110_pll_set_rate(struct clk_jh7110_pllx *pll,
        PLLX_SET(pll->offset->dsmpd, pll->offset->dsmpd_mask, 1);
        PLLX_SET(pll->offset->prediv, pll->offset->prediv_mask, rate->prediv);
        PLLX_SET(pll->offset->fbdiv, pll->offset->fbdiv_mask, rate->fbdiv);
-       PLLX_SET(pll->offset->postdiv1, pll->offset->postdiv1, 0);
+       PLLX_SET(pll->offset->postdiv1, pll->offset->postdiv1_mask, 0);
        PLLX_SET(pll->offset->pd, pll->offset->pd_mask, PLL_PD_ON);
 
        if (set) {