arm: rmobile: r8a7794: Enable SMP mode of Auxiliary Control Register

r8a7794 uses ARM SoC of CA7 base. If we want to use dcache on CA7, we
need to enable SMP bit of Auxiliary Control Register.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
index d47546a11d7ad61def4ec26e2ca27171698c71ad..a5dbbea9e1527d79f26348d939735408bd65e4ef 100644 (file)
--- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
+++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
@@ -40,7 +40,7 @@ do_lowlevel_init:
        and     r1, r1, #0x7F00
        lsrs    r1, r1, #8
        cmp     r1, #0x4C               /* 0x4C is ID of r8a7794 */
-       beq     _exit_init_l2_a15
+       beq     _enable_actlr_smp
 
        /* surpress wfe if ca15 */
        tst r4, #4
@@ -64,6 +64,16 @@ do_lowlevel_init:
        orrne r0, r0, #0x20             /* L2CTLR[5] */
 #endif
        mcrne p15, 1, r0, c9, c0, 2
+
+       b       _exit_init_l2_a15
+
+_enable_actlr_smp: /* R8A7794 only (CA7) */
+#ifndef CONFIG_DCACHE_OFF
+       mrc    p15, 0, r0, c1, c0, 1
+       orr    r0, r0, #0x40
+       mcr    p15, 0, r0, c1, c0, 1
+#endif
+
 _exit_init_l2_a15:
        ldr     r3, =(CONFIG_SYS_INIT_SP_ADDR)
        sub     sp, r3, #4