]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
armv8: layerscape: properly use CPU_RELEASE_ADDR
authorMichael Walle <michael@walle.cc>
Mon, 1 Jun 2020 19:53:26 +0000 (21:53 +0200)
committerPriyanka Jain <priyanka.jain@nxp.com>
Mon, 27 Jul 2020 08:46:27 +0000 (14:16 +0530)
The generic armv8 code already has support to bring up the secondary
cores. Thus, don't hardcode the jump in the layerscape lowlevel_init to
the spin table code; instead just return early and let the common armv8
code handle the jump. This way we can actually use the CPU_RELEASE_ADDR
feature.

Signed-off-by: Michael Walle <michael@walle.cc>
[Rebased, Removed kontron_sl28.h change as file does not exist]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
arch/arm/include/asm/arch-fsl-layerscape/mp.h
include/configs/ls1028a_common.h
include/configs/ls1043a_common.h
include/configs/ls1046a_common.h
include/configs/ls1088a_common.h
include/configs/ls2080a_common.h
include/configs/lx2160a_common.h

index 2a8d592cc5c378ff307b352c253ee898f0273a80..d75013eb9c8dd800f909e0cc5b6c34568bb0d44d 100644 (file)
@@ -208,8 +208,13 @@ ENTRY(lowlevel_init)
        branch_if_master x0, x1, 2f
 
 #if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
-       ldr     x0, =secondary_boot_func
-       blr     x0
+       /*
+        * Formerly, here was a jump to secondary_boot_func, but we just
+        * return early here and let the generic code in start.S handle
+        * the jump to secondary_boot_func.
+        */
+       mov     lr, x29                 /* Restore LR */
+       ret
 #endif
 
 2:
@@ -421,6 +426,11 @@ ENDPROC(__asm_flush_l3_dcache)
 #endif /* CONFIG_SYS_FSL_HAS_CCN504 */
 
 #ifdef CONFIG_MP
+       .align 3
+       .global secondary_boot_addr
+secondary_boot_addr:
+       .quad secondary_boot_func
+
        /* Keep literals not used by the secondary boot code outside it */
        .ltorg
 
index 00aa91b0a20c60bf3c334d4ea940413558787d6b..623977651a95ff93aec456007722b27fa00051f8 100644 (file)
@@ -43,7 +43,6 @@ static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; }
 #endif
 void *get_spin_tbl_addr(void);
 phys_addr_t determine_mp_bootpg(void);
-void secondary_boot_func(void);
 int is_core_online(u64 cpu_id);
 u32 cpu_pos_mask(void);
 #endif
index fe4a87b6972b20597a90e2785a18405e2c6e83ee..4863fb2b643f2bfaacbd99512a027f778cd6798a 100644 (file)
@@ -28,7 +28,7 @@
 /*
  * SMP Definitinos
  */
-#define CPU_RELEASE_ADDR               secondary_boot_func
+#define CPU_RELEASE_ADDR               secondary_boot_addr
 
 /* Generic Timer Definitions */
 #define COUNTER_FREQUENCY              25000000        /* 25MHz */
index 3efac1fa7800aa0b18a76c623d2193d214b61038..1271d706108af4efb0f638929d59cd5cbb5d9838 100644 (file)
@@ -47,7 +47,7 @@
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
 
-#define CPU_RELEASE_ADDR               secondary_boot_func
+#define CPU_RELEASE_ADDR               secondary_boot_addr
 
 /* Generic Timer Definitions */
 #define COUNTER_FREQUENCY              25000000        /* 25MHz */
index 8fe6937dfbc602bdc3077c8db96e411e5ee829e2..5899e32c2133f5bcdd8b86ab299b436d3afe3afe 100644 (file)
@@ -48,7 +48,7 @@
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
 
-#define CPU_RELEASE_ADDR               secondary_boot_func
+#define CPU_RELEASE_ADDR               secondary_boot_addr
 
 /* Generic Timer Definitions */
 #define COUNTER_FREQUENCY              25000000        /* 25MHz */
index 3ea16752de09fc7119887242227b6fa853ee0dfe..5b83e61ab23aff61116147f69e220a5aa238de4a 100644 (file)
@@ -48,7 +48,7 @@
 /*
  * SMP Definitinos
  */
-#define CPU_RELEASE_ADDR               secondary_boot_func
+#define CPU_RELEASE_ADDR               secondary_boot_addr
 
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 2048 * 1024)
index 410872dfd86508d58dd97ab5998bac307d9e8197..d93ff291bdc35f40b4d8027c58ddf5270dcdb5ef 100644 (file)
@@ -42,7 +42,7 @@
 /*
  * SMP Definitinos
  */
-#define CPU_RELEASE_ADDR               secondary_boot_func
+#define CPU_RELEASE_ADDR               secondary_boot_addr
 
 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
index 9bc287f7aa4313731172dd10733fc8a3c6e21dc2..0c3d6835516654b6d9b28509343f678dff3b78c2 100644 (file)
@@ -52,7 +52,7 @@
 #define CONFIG_SYS_LOAD_ADDR   (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 
 /* SMP Definitinos  */
-#define CPU_RELEASE_ADDR               secondary_boot_func
+#define CPU_RELEASE_ADDR               secondary_boot_addr
 
 /* Generic Timer Definitions */
 /*