clk: stm32mp1: fix CK_MPU calculation

When the CK_MPU used PLL1_MPUDIV, the current rate is
wrong. The clock must use stm32mp1_mpu_div as a shift
value. Fix the check value used to enter PLL_MPUDIV.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 50df8425bf763b85d6200693a9094dc44e72f7c8..0d0ea43fd201ad02c7aa83b1095a417b8e553a67 100644 (file)
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -954,10 +954,11 @@ static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
                case RCC_MPCKSELR_PLL:
                case RCC_MPCKSELR_PLL_MPUDIV:
                        clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
-                       if (p == RCC_MPCKSELR_PLL_MPUDIV) {
+                       if ((reg & RCC_SELR_SRC_MASK) ==
+                           RCC_MPCKSELR_PLL_MPUDIV) {
                                reg = readl(priv->base + RCC_MPCKDIVR);
-                               clock /= stm32mp1_mpu_div[reg &
-                                                         RCC_MPUDIV_MASK];
+                               clock >>= stm32mp1_mpu_div[reg &
+                                       RCC_MPUDIV_MASK];
                        }
                        break;
                }