clk: sunxi: Add Allwinner H6 CLK driver

Add initial clock driver for Allwinner H6.

- Implement UART bus clocks via ccu_clk_gate table for
  H6, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for H6,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>

diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index a6f84e9e56af3f417d42a1a838f2568958f922e1..cb11c7c21e115f18c5d48438809a9ee3109be1b2 100644 (file)
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -65,6 +65,13 @@ config CLK_SUN8I_H3
          This enables common clock driver support for platforms based
          on Allwinner H3/H5 SoC.
 
+config CLK_SUN50I_H6
+       bool "Clock driver for Allwinner H6"
+       default MACH_SUN50I_H6
+       help
+         This enables common clock driver support for platforms based
+         on Allwinner H6 SoC.
+
 config CLK_SUN50I_A64
        bool "Clock driver for Allwinner A64"
        default MACH_SUN50I

diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index fbd43527a6cba156bd00cbe73ce4931bd5e29ff6..794aa2461c7c9d6d6ca07fde035ef2ecd74b6cd7 100644 (file)
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -14,4 +14,5 @@ obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
 obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
 obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
+obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
new file mode 100644 (file)
index 0000000..0da3a40
--- /dev/null
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun50i-h6-ccu.h>
+#include <dt-bindings/reset/sun50i-h6-ccu.h>
+
+static struct ccu_clk_gate h6_gates[] = {
+       [CLK_BUS_UART0]         = GATE(0x90c, BIT(0)),
+       [CLK_BUS_UART1]         = GATE(0x90c, BIT(1)),
+       [CLK_BUS_UART2]         = GATE(0x90c, BIT(2)),
+       [CLK_BUS_UART3]         = GATE(0x90c, BIT(3)),
+};
+
+static struct ccu_reset h6_resets[] = {
+       [RST_BUS_UART0]         = RESET(0x90c, BIT(16)),
+       [RST_BUS_UART1]         = RESET(0x90c, BIT(17)),
+       [RST_BUS_UART2]         = RESET(0x90c, BIT(18)),
+       [RST_BUS_UART3]         = RESET(0x90c, BIT(19)),
+};
+
+static const struct ccu_desc h6_ccu_desc = {
+       .gates = h6_gates,
+       .resets = h6_resets,
+};
+
+static int h6_clk_bind(struct udevice *dev)
+{
+       return sunxi_reset_bind(dev, ARRAY_SIZE(h6_resets));
+}
+
+static const struct udevice_id h6_ccu_ids[] = {
+       { .compatible = "allwinner,sun50i-h6-ccu",
+         .data = (ulong)&h6_ccu_desc },
+       { }
+};
+
+U_BOOT_DRIVER(clk_sun50i_h6) = {
+       .name           = "sun50i_h6_ccu",
+       .id             = UCLASS_CLK,
+       .of_match       = h6_ccu_ids,
+       .priv_auto_alloc_size   = sizeof(struct ccu_priv),
+       .ops            = &sunxi_clk_ops,
+       .probe          = sunxi_clk_probe,
+       .bind           = h6_clk_bind,
+};