imx: mx6: ddr correct tRFC and tXS

To Chip density 4Gb, tRFC should be 300ns, see
"Table 61 — Refresh parameters by device density" of JESD79-3E.
tXS(min) is max(5nCK, tRFC(min) + 10ns).

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 28fa3cf6482c9de787d83df187cefa03f5cfd2dd..3ec3e791c94d2fbb1012f771bd709970a1010ecf 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -357,8 +357,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
                txs = DIV_ROUND_UP(170000, clkper) - 1;
                break;
        case 4: /* 4Gb per chip */
-               trfc = DIV_ROUND_UP(260000, clkper) - 1;
-               txs = DIV_ROUND_UP(270000, clkper) - 1;
+               trfc = DIV_ROUND_UP(300000, clkper) - 1;
+               txs = DIV_ROUND_UP(310000, clkper) - 1;
                break;
        case 8: /* 8Gb per chip */
                trfc = DIV_ROUND_UP(350000, clkper) - 1;