ARM: dts: stm32: set PLL4_P to 125Mhz for ETH_CLK for stm32mp157c-odyssey

Odyssey board requires ETH_CLK of 125Mhz. This commit sets PLL4_P/Q/R to
125, 62.5 and 62.5Mhz in respectively.

Signed-off-by: Heesub Shin <heesub@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>

diff --git a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
index b780dbd95e2cedfc623f50d969073e524c073537..d07fdcf4bc382dcd2e6605f96e5795e9703dedb4 100644 (file)
--- a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
@@ -115,11 +115,11 @@
                bootph-all;
        };
 
-       /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
+       /* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */
        pll4: st,pll@3 {
                compatible = "st,stm32mp1-pll";
                reg = <3>;
-               cfg = < 3 98 5 7 7 PQR(1,1,1) >;
+               cfg = < 3 124 5 9 9 PQR(1,1,1) >;
                bootph-all;
        };
 };