clock-snapdragon: Add clk_rcg_set_rate() with mnd_width=0

Add clk_rcg_set_rate() which allows to configure clocks without programming
MND values. This is required for configuring I2C clocks on QCS404.

Co-developed-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c
index fda7098274f808d3bed2d4aefe8325c037e1af88..0ac45dce9a9218c727245575b441212e3ecac27b 100644 (file)
--- a/arch/arm/mach-snapdragon/clock-snapdragon.c
+++ b/arch/arm/mach-snapdragon/clock-snapdragon.c
@@ -111,6 +111,30 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
        clk_bcr_update(base + regs->cmd_rcgr);
 }
 
+/* root set rate for clocks with half integer and mnd_width=0 */
+void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div,
+                     int source)
+{
+       u32 cfg;
+
+       /* setup src select and divider */
+       cfg  = readl(base + regs->cfg_rcgr);
+       cfg &= ~CFG_MASK;
+       cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
+
+       /*
+        * Set the divider; HW permits fraction dividers (+0.5), but
+        * for simplicity, we will support integers only
+        */
+       if (div)
+               cfg |= (2 * div - 1) & CFG_DIVIDER_MASK;
+
+       writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
+
+       /* Inform h/w to start using the new config. */
+       clk_bcr_update(base + regs->cmd_rcgr);
+}
+
 static int msm_clk_probe(struct udevice *dev)
 {
        struct msm_clk_priv *priv = dev_get_priv(dev);

diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h b/arch/arm/mach-snapdragon/clock-snapdragon.h
index 2ac53b538dc682fe99830e93d888e3749947cfae..c90bbefa58819572e52c4d775f7961887a56eb27 100644 (file)
--- a/arch/arm/mach-snapdragon/clock-snapdragon.h
+++ b/arch/arm/mach-snapdragon/clock-snapdragon.h
@@ -42,5 +42,7 @@ void clk_enable_cbc(phys_addr_t cbcr);
 void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk);
 void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
                          int div, int m, int n, int source);
+void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div,
+                     int source);
 
 #endif