Makefile: Run defconfig files through the C preprocessor

This allows us to use some of the normal preprocessor directives inside
defconfig files. Such as #define and #include.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Nishanth Menon <nm@ti.com>

diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile
index 2d97aab8d21e881ff427f77bf9dbdb90e1a3a8cc..5ce5845e8247eb64b5efe1cf188cc40157d61237 100644 (file)
--- a/scripts/kconfig/Makefile
+++ b/scripts/kconfig/Makefile
@@ -93,7 +93,8 @@ endif
 endif
 
 %_defconfig: $(obj)/conf
-       $(Q)$< $(silent) --defconfig=arch/$(SRCARCH)/configs/$@ $(Kconfig)
+       $(Q)$(CPP) -nostdinc -I $(srctree) -undef -x assembler-with-cpp $(srctree)/arch/$(SRCARCH)/configs/$@ -o generated_defconfig
+       $(Q)$< $(silent) --defconfig=generated_defconfig $(Kconfig)
 
 # Added for U-Boot (backward compatibility)
 %_config: %_defconfig