#include <asm/io.h>
#include <common.h>
+#include <clk.h>
#include <dm/device.h>
#include <dm/fdtaddr.h>
#include <dm/read.h>
struct sp805_wdt_priv {
void __iomem *reg;
+ unsigned long clk_rate;
};
static int sp805_wdt_reset(struct udevice *dev)
* set 120s, the gd->bus_clk is less than 1145MHz, the load_value will
* not overflow.
*/
- load_value = (gd->bus_clk) /
- (2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time;
+ if (gd->bus_clk) {
+ load_value = (gd->bus_clk) /
+ (2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time;
+ } else {
+ /* platform provide clk */
+ load_value = (timeout / 2) * (priv->clk_rate / 1000);
+ }
writel(UNLOCK, priv->reg + WDTLOCK);
writel(load_value, priv->reg + WDTLOAD);
static int sp805_wdt_ofdata_to_platdata(struct udevice *dev)
{
struct sp805_wdt_priv *priv = dev_get_priv(dev);
+ struct clk clk;
priv->reg = (void __iomem *)dev_read_addr(dev);
if (IS_ERR(priv->reg))
return PTR_ERR(priv->reg);
+ if (!clk_get_by_index(dev, 0, &clk))
+ priv->clk_rate = clk_get_rate(&clk);
+
return 0;
}