clkdiv(CFG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) |
clkdiv(CFG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) |
clkdiv(CFG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) |
- clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) |
+ clkdiv(CFG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) |
clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0),
&lpc32xx_nand_mlc_registers->time_reg);
}
#define CFG_LPC32XX_NAND_MLC_NAND_TA 18181818
#define CFG_LPC32XX_NAND_MLC_RD_HIGH 31250000
#define CFG_LPC32XX_NAND_MLC_RD_LOW 45454545
-#define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000
+#define CFG_LPC32XX_NAND_MLC_WR_HIGH 40000000
#define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333
/*