]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
imx: drop CONFIG_MXC_UART_BASE
authorPeng Fan <peng.fan@nxp.com>
Sat, 11 Jun 2022 12:20:54 +0000 (20:20 +0800)
committerStefano Babic <sbabic@denx.de>
Tue, 14 Jun 2022 19:33:13 +0000 (21:33 +0200)
Since these boards has CONFIG_DM_SERIAL and/or CONFIG_SPL_DM_SERIAL,
the legacy macro no need to be defined.

Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Soeren Moch <smoch@web.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
13 files changed:
include/configs/aristainetos2.h
include/configs/imx8mm_evk.h
include/configs/imx8mm_venice.h
include/configs/imx8mn_bsh_smm_s2_common.h
include/configs/imx8mn_evk.h
include/configs/imx8mn_venice.h
include/configs/imx8mp_evk.h
include/configs/imx8mp_venice.h
include/configs/mx7dsabresd.h
include/configs/somlabs_visionsom_6ull.h
include/configs/tbs2910.h
include/configs/verdin-imx8mm.h
include/configs/verdin-imx8mp.h

index 026775de7c56c90684831c4da0a2dd5f13aeca8f..de4f4407abb8bba83ba6fb3ae59fd93c32eb65fd 100644 (file)
 #define CONFIG_HOSTNAME                "aristainetos2"
 
 #if (CONFIG_SYS_BOARD_VERSION == 5)
-#define CONFIG_MXC_UART_BASE   UART2_BASE
 #define CONSOLE_DEV    "ttymxc1"
 #elif (CONFIG_SYS_BOARD_VERSION == 6)
-#define CONFIG_MXC_UART_BASE   UART1_BASE
 #define CONSOLE_DEV    "ttymxc0"
 #endif
 
index 983743b509368918a298ab7b7ebf040450fbe94f..6da09deba85cc3b8b1dadc1311a918536c061bc5 100644 (file)
@@ -57,8 +57,6 @@
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE                        0x80000000 /* 2GB DDR */
 
-#define CONFIG_MXC_UART_BASE           UART_BASE_ADDR(2)
-
 #define CONFIG_FEC_MXC_PHYADDR          0
 
 #endif
index 595c1074966822600fee326193c1ea62147e30b7..7a2ef8f533bf1da449b73adfa5f3409519b98bb0 100644 (file)
@@ -90,9 +90,6 @@
 #define PHYS_SDRAM_SIZE                        SZ_4G
 #define CONFIG_SYS_BOOTM_LEN           SZ_256M
 
-/* UART */
-#define CONFIG_MXC_UART_BASE           UART_BASE_ADDR(2)
-
 /* FEC */
 #define CONFIG_FEC_MXC_PHYADDR          0
 #define FEC_QUIRK_ENET_MAC
index 5bdbd37e9cb9b905ff9ccaa1cd47fb18fd5ba6f5..63f7da740ef1fe2a0ad48ab9544e67bd070c11df 100644 (file)
@@ -32,8 +32,4 @@
 #define CONFIG_SYS_SDRAM_BASE          0x40000000
 #define PHYS_SDRAM                     0x40000000
 
-#define CONFIG_MXC_UART_BASE           UART4_BASE_ADDR
-
-/* I2C */
-
 #endif /* __IMX8MN_BSH_SMM_S2_COMMON_H */
index 73ba49b0d8fbd90d80e64958c5f72aa865c3449e..506d1ffd5a689890a6bb705067d7d745edc60165 100644 (file)
@@ -64,6 +64,4 @@
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE                        0x80000000 /* 2GB DDR */
 
-#define CONFIG_MXC_UART_BASE           UART_BASE_ADDR(2)
-
 #endif
index 8565ba7fdb15b27dbab3f9e83ff27a429bcfb7d7..8c45c8462c2d7af73bf4664c3876c7c48e11ace5 100644 (file)
@@ -86,9 +86,6 @@
 #define PHYS_SDRAM_SIZE                        SZ_4G
 #define CONFIG_SYS_BOOTM_LEN           SZ_256M
 
-/* UART */
-#define CONFIG_MXC_UART_BASE           UART_BASE_ADDR(2)
-
 /* FEC */
 #define CONFIG_FEC_MXC_PHYADDR          0
 #define FEC_QUIRK_ENET_MAC
index 65c1616bca723d7c1e583d1c6527e037a67f7cef..465e1cb4a7e9dc3fb6235c4af7f5f9cf87236d61 100644 (file)
@@ -69,6 +69,4 @@
 #define PHYS_SDRAM_2                   0x100000000
 #define PHYS_SDRAM_2_SIZE              0xC0000000      /* 3 GB */
 
-#define CONFIG_MXC_UART_BASE           UART_BASE_ADDR(2)
-
 #endif
index e1d33553956842da67af32237aa4ab4bb75d744c..d9baffb3a24d4513cd0644034f7969919324aad4 100644 (file)
@@ -86,9 +86,6 @@
 #define PHYS_SDRAM_SIZE                        SZ_4G
 #define CONFIG_SYS_BOOTM_LEN           SZ_256M
 
-/* UART */
-#define CONFIG_MXC_UART_BASE           UART2_BASE_ADDR
-
 /* FEC */
 #define FEC_QUIRK_ENET_MAC
 
index 36cef252ea22efaa699b62247d1a01dd6c77dedb..a6b8c275fe779c444e33a7d3597819cbcb898bbe 100644 (file)
@@ -12,7 +12,6 @@
 
 #define PHYS_SDRAM_SIZE                        SZ_1G
 
-#define CONFIG_MXC_UART_BASE            UART1_IPS_BASE_ADDR
 
 #ifdef CONFIG_IMX_BOOTAUX
 /* Set to QSPI1 A flash at default */
index 98966cfeb91d42155e03405a5de627db5ce66c97..f1886cb214599d6b0709eed873af227a1dcc97a1 100644 (file)
@@ -16,7 +16,6 @@
 /* SPL options */
 #include "imx6_spl.h"
 
-#define CONFIG_MXC_UART_BASE           UART1_BASE
 
 /* MMC Configs */
 #ifdef CONFIG_FSL_USDHC
index 1ebe28b7c1ba15e9469f62fb97bbc4089b977ced..c355083519f3b04040a059250afbfeb277c0bfce 100644 (file)
@@ -20,9 +20,6 @@
 
 #define CONFIG_SYS_BOOTMAPSZ           0x10000000
 
-/* Serial console */
-#define CONFIG_MXC_UART_BASE           UART1_BASE /* select UART1/UART2 */
-
 /* Framebuffer */
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
index 8f464dd39f0b53757e090dcba01c19e985b07c80..4fb0d69f57910b6df6121316f7677df8dd5b7f7d 100644 (file)
@@ -72,9 +72,6 @@
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE                        SZ_2G /* 2GB DDR */
 
-/* UART */
-#define CONFIG_MXC_UART_BASE           UART_BASE_ADDR(1)
-
 /* ENET */
 #define CONFIG_FEC_MXC_PHYADDR          7
 
index 906a20fd8402fc49a736397fa98e5a1586895d82..704a0538a9c42a3fa5fba370ed04ce355b931932 100644 (file)
@@ -89,7 +89,4 @@
 #define PHYS_SDRAM_2                   0x100000000
 #define PHYS_SDRAM_2_SIZE              (SZ_4G + SZ_1G)
 
-/* UART */
-#define CONFIG_MXC_UART_BASE           UART_BASE_ADDR(3)
-
 #endif /* __VERDIN_IMX8MP_H */