pci: renesas: Fix BAR mapping on Gen3

Because the first PCIExAR(n) register is configured with the mapping,
It is the second PCIExAR(n) register that must be written with 0, not
the last one. Update the n from 4 to 1 to select the correct register.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c
index 6b08409b85d1a344553aba67cb7587dce7e51bb2..34a561ef8b4beb50e4d0df261f6da62df7821435 100644 (file)
--- a/drivers/pci/pci-rcar-gen3.c
+++ b/drivers/pci/pci-rcar-gen3.c
@@ -358,9 +358,9 @@ static int rcar_gen3_pcie_probe(struct udevice *dev)
                break;
        }
 
-       writel(0, priv->regs + PCIEPRAR(4));
-       writel(0, priv->regs + PCIELAR(4));
-       writel(0, priv->regs + PCIELAMR(4));
+       writel(0, priv->regs + PCIEPRAR(1));
+       writel(0, priv->regs + PCIELAR(1));
+       writel(0, priv->regs + PCIELAMR(1));
 
        ret = rcar_gen3_pcie_hw_init(dev);
        if (ret)