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imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers
authorYe Li <ye.li@nxp.com>
Tue, 31 Jan 2023 08:42:21 +0000 (16:42 +0800)
committerStefano Babic <sbabic@denx.de>
Wed, 29 Mar 2023 18:15:42 +0000 (20:15 +0200)
commit4e08a510d23e2e23c8a776ccea582d0acd75fd4d
tree531df17303054600555777b003d5c86ac86f3295tree | snapshot
parente01d1b1e302f77bdad6d1f0c7a17c4edee1e7ebdcommit | diff
imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers

At present, in cgc1_pll3_init we don't set the pll3pfd div values,
just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2
to 1 and pfd2div1 to 3.
This finally causes some clocks' rate decreased, for example USDHC.
So clear the PLL3DIV_PFD dividers to get correct rate.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
arch/arm/mach-imx/imx8ulp/cgc.c diff | blob | history
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