From d31f1c9236973a463a73cd2748bcc62939fc9247 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 18 Feb 2020 08:38:06 +0100 Subject: [PATCH] arm64: zynqmp: Update Copyright years to 2020 Trivial change. Signed-off-by: Michal Simek --- arch/arm/dts/avnet-ultra96-rev1.dts | 2 +- arch/arm/dts/zynqmp-clk-ccf.dtsi | 2 +- arch/arm/dts/zynqmp-clk.dtsi | 2 +- arch/arm/dts/zynqmp-mini-qspi.dts | 2 +- arch/arm/dts/zynqmp-zc1232-revA.dts | 2 +- arch/arm/dts/zynqmp-zc1254-revA.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 2 +- arch/arm/dts/zynqmp-zcu100-revC.dts | 2 +- arch/arm/dts/zynqmp-zcu102-rev1.0.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revB.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revC.dts | 2 +- arch/arm/dts/zynqmp-zcu106-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu111-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu1275-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu1275-revB.dts | 2 +- arch/arm/dts/zynqmp-zcu1285-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu208-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu216-revA.dts | 2 +- arch/arm/dts/zynqmp.dtsi | 2 +- 25 files changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm/dts/avnet-ultra96-rev1.dts b/arch/arm/dts/avnet-ultra96-rev1.dts index 88aa06fa78..ddb8febaec 100644 --- a/arch/arm/dts/avnet-ultra96-rev1.dts +++ b/arch/arm/dts/avnet-ultra96-rev1.dts @@ -2,7 +2,7 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 8eacd22d7c..1098e89019 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -2,7 +2,7 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi index c9464ec8eb..82eac56c9d 100644 --- a/arch/arm/dts/zynqmp-clk.dtsi +++ b/arch/arm/dts/zynqmp-clk.dtsi @@ -2,7 +2,7 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts index e4ba5ae9b6..c523e81236 100644 --- a/arch/arm/dts/zynqmp-mini-qspi.dts +++ b/arch/arm/dts/zynqmp-mini-qspi.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP Mini Configuration * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2020, Xilinx, Inc. * * Siva Durga Prasad * Michal Simek diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts index 6117f83c47..87152afc32 100644 --- a/arch/arm/dts/zynqmp-zc1232-revA.dts +++ b/arch/arm/dts/zynqmp-zc1232-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts index 6ac8346d23..d6b2834f3a 100644 --- a/arch/arm/dts/zynqmp-zc1254-revA.dts +++ b/arch/arm/dts/zynqmp-zc1254-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2020, Xilinx, Inc. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index bb6a94eefb..d604cf1342 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 1cc8aaa879..2ff7952e70 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index 2ead8dd24d..c7de59e1e9 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index 84c2904dc2..13508c4519 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index 12c0173c55..8d8ebeaac3 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2020, Xilinx, Inc. * * Siva Durga Prasad * Michal Simek diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 21118c8cc3..1726edf78e 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016 - 2020, Xilinx, Inc. * * Michal Simek * Nathalie Chan King Choy diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts index 6c702f2674..f39013794f 100644 --- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts +++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index b580f9263d..222b67c7ce 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index 38ec188164..2422558b74 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 82557c88d2..6375b47ff8 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index e0e7dac010..425d7605bf 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index d31982fce7..dc533f5f6d 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index bff224f78d..1304c509ac 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index c22de576a5..8755bc433b 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU1275 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017 - 2020, Xilinx, Inc. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index 2ec29b0b5d..16f609c7e5 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018 - 2020, Xilinx, Inc. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts index 9c18013138..8a4d5b9fed 100644 --- a/arch/arm/dts/zynqmp-zcu1285-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU1285 RevA * - * (C) Copyright 2018 - 2019, Xilinx, Inc. + * (C) Copyright 2018 - 2020, Xilinx, Inc. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 85f9e1f628..7395f23b67 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU208 * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index 2db546fddd..f08bbe36c2 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU216 * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017 - 2020, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 9e7fae83f7..ec0dd73e15 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014 - 2020, Xilinx, Inc. * * Michal Simek * -- 2.39.5