From c64afba2fb483d416ad5da9dfe3f1f156ccf2366 Mon Sep 17 00:00:00 2001
From: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Date: Thu, 5 Apr 2018 05:19:27 -0700
Subject: [PATCH] fpga: zynqpl: Check if aes engine is enabled
AES engine cannot be used if has not been enabled at boot time
with an encrypted boot image.
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/fpga/zynqpl.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index de71969399..90bb850833 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -22,6 +22,7 @@
#define DEVCFG_CTRL_PCFG_PROG_B 0x40000000
#define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000
#define DEVCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000
+#define DEVCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00
#define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
#define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
#define DEVCFG_ISR_RX_FIFO_OV 0x00040000
@@ -522,6 +523,13 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
return FPGA_FAIL;
}
+ /* Check AES engine is enabled */
+ if (!(readl(&devcfg_base->ctrl) &
+ DEVCFG_CTRL_PCFG_AES_EN_MASK)) {
+ printf("%s: AES engine is not enabled\n", __func__);
+ return FPGA_FAIL;
+ }
+
if (zynq_dma_xfer_init(bstype)) {
printf("%s: zynq_dma_xfer_init FAIL\n", __func__);
return FPGA_FAIL;
--
2.39.5