From 5865d14dde8f60f678e144e432a5e5ad223915d0 Mon Sep 17 00:00:00 2001
From: Jian Li <jian.li@nxp.com>
Date: Mon, 20 Jan 2020 15:14:42 +0800
Subject: [PATCH] imx8mp: DDR performance tunning
1. set SCHED.rdwr_idle_gap=0
2. set SCHED.pageclose=1
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Jian Li <jian.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
board/freescale/imx8mp_evk/lpddr4_timing.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c
index 6b17b3f141..75d6b530d2 100644
--- a/board/freescale/imx8mp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8mp_evk/lpddr4_timing.c
@@ -52,7 +52,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0x68070707 },
{ 0x3d40021c, 0xf08 },
- { 0x3d400250, 0x29001701 },
+ { 0x3d400250, 0x00001705 },
{ 0x3d400254, 0x2c },
{ 0x3d40025c, 0x4000030 },
{ 0x3d400264, 0x900093e7 },
--
2.39.5