From 4f2532c4a4a34f0241ef9bc921044772f19f928d Mon Sep 17 00:00:00 2001
From: York Sun <yorksun@freescale.com>
Date: Tue, 6 Jan 2015 13:19:01 -0800
Subject: [PATCH] armv8/ls2085a_emu: Enable sync of refresh

Enable sync of DDR refresh for LS2085a platform. GPP DDR controllers
stay in sync. DP-DDR has only one controller so it does no harm.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 include/configs/ls2085a_emu.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/ls2085a_emu.h b/include/configs/ls2085a_emu.h
index 2d2e1ea0bd..a02d69450b 100644
--- a/include/configs/ls2085a_emu.h
+++ b/include/configs/ls2085a_emu.h
@@ -20,4 +20,5 @@
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
 #define CONFIG_SYS_SPD_BUS_NUM	1	/* SPD on I2C bus 1 */
 
+#define CONFIG_FSL_DDR_SYNC_REFRESH
 #endif /* __LS2_EMU_H */
-- 
2.39.5