From 4d5723da57344cc8f41324fb18b039fb2ce83428 Mon Sep 17 00:00:00 2001
From: Kumar Gala <galak@kernel.crashing.org>
Date: Fri, 17 Dec 2010 07:01:00 -0600
Subject: [PATCH] powerpc/85xx: Rework P2020DS pci_init_board to use common FSL
PCIe code
Remove duplicated code in P2020DS board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
board/freescale/p2020ds/law.c | 8 +--
board/freescale/p2020ds/p2020ds.c | 105 +-----------------------------
include/configs/P2020DS.h | 3 +
3 files changed, 5 insertions(+), 111 deletions(-)
diff --git a/board/freescale/p2020ds/law.c b/board/freescale/p2020ds/law.c
index 28ed2ed5ee..91642a9837 100644
--- a/board/freescale/p2020ds/law.c
+++ b/board/freescale/p2020ds/law.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -29,12 +29,6 @@
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
- SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
- SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
- SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
- SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
- SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
};
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index 40589da117..8546aa903f 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -155,113 +155,10 @@ phys_size_t fixed_sdram(void)
#endif
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
-
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
-
-#ifdef CONFIG_PCIE3
-static struct pci_controller pcie3_hose;
-#endif
-
#ifdef CONFIG_PCI
void pci_init_board(void)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- struct fsl_pci_info pci_info[3];
- u32 devdisr, pordevsr, io_sel;
- int first_free_busno = 0;
- int num = 0;
-
- int pcie_ep, pcie_configured;
-
- devdisr = in_be32(&gur->devdisr);
- pordevsr = in_be32(&gur->pordevsr);
- io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-
- debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
-
- puts("\n");
-#ifdef CONFIG_PCIE2
- pcie_configured = is_serdes_configured(PCIE2);
-
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
- SET_STD_PCIE_INFO(pci_info[num], 2);
- pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
- printf("PCIE2: connected to ULI as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
- first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno);
-
- /*
- * The workaround doesn't work on p2020 because the location
- * we try and read isn't valid on p2020, fix this later
- */
-#if 0
- /*
- * Activate ULI1575 legacy chip by performing a fake
- * memory access. Needed to make ULI RTC work.
- * Device 1d has the first on-board memory BAR.
- */
-
- pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0),
- PCI_BASE_ADDRESS_1, &temp32);
- if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
- void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
- temp32, 4, 0);
- debug(" uli1575 read to %p\n", p);
- in_be32(p);
- }
-#endif
- } else {
- printf("PCIE2: disabled\n");
- }
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE3
- pcie_configured = is_serdes_configured(PCIE3);
-
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
- SET_STD_PCIE_INFO(pci_info[num], 3);
- pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
- printf("PCIE3: connected to Slot 1 as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
- first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie3_hose, first_free_busno);
- } else {
- printf("PCIE3: disabled\n");
- }
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE1
- pcie_configured = is_serdes_configured(PCIE1);
-
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
- SET_STD_PCIE_INFO(pci_info[num], 1);
- pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
- printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
- first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno);
- } else {
- printf("PCIE1: disabled\n");
- }
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
-#endif
+ fsl_pcie_init_board(0);
}
#endif
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index 0af21528d9..24f2498d07 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -394,6 +394,7 @@
*/
/* controller 3, Slot 1, tgtid 3, Base address b000 */
+#define CONFIG_SYS_PCIE3_NAME "Slot 1"
#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
@@ -413,6 +414,7 @@
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME "ULI"
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
@@ -432,6 +434,7 @@
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 1, Slot 2, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME "Slot 2"
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
--
2.39.5