From 3f63d27c177a84dd97f77fb843ff4e4c6d7d45eb Mon Sep 17 00:00:00 2001
From: Jian Li <jian.li@nxp.com>
Date: Thu, 27 Feb 2020 09:40:10 +0800
Subject: [PATCH] imx8mp: Disables use of MR4 TUF flag (MR4[7]) bit
In uMCTL2 Databook, for LPDDR4, it is recommended to set
this register to 1. This can avoid ddr bandwidth is lower
after booting with running for a while.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jian Li <jian.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
board/freescale/imx8mp_evk/lpddr4_timing.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c
index 75d6b530d2..7658262b37 100644
--- a/board/freescale/imx8mp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8mp_evk/lpddr4_timing.c
@@ -11,7 +11,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400304, 0x1 },
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa3080020 },
- { 0x3d400020, 0x323 },
+ { 0x3d400020, 0x1323 },
{ 0x3d400024, 0x1e84800 },
{ 0x3d400064, 0x7a0118 },
{ 0x3d4000d0, 0xc00307a3 },
--
2.39.5