From 1ba80d1b2ce474e0e924bc9c0c1b44d3554204b1 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 3 Jul 2023 18:06:54 +0300 Subject: [PATCH] ARM: tegra: clock: support get and set rate for simple PLL Simple PLL clocks like PLLD2 were omitted since they do not share common 4 register structure with main clocks. Such clocks are containd in simple PLL group. Only clock_start_pll function supported them. This patch expands this support on clock_set_rate and clock_get_rate which should make simple PLL clocks equal to main PLL clocks. Signed-off-by: Svyatoslav Ryhel --- arch/arm/mach-tegra/clock.c | 75 +++++++++++++++++++++------- arch/arm/mach-tegra/tegra114/clock.c | 15 ++++++ arch/arm/mach-tegra/tegra124/clock.c | 12 +++-- arch/arm/mach-tegra/tegra20/clock.c | 15 ++++++ arch/arm/mach-tegra/tegra210/clock.c | 15 ++++++ arch/arm/mach-tegra/tegra30/clock.c | 15 ++++++ 6 files changed, 126 insertions(+), 21 deletions(-) diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 966009f375..7f31630a23 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -128,14 +128,14 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, struct clk_pll_simple *simple_pll = NULL; u32 misc_data, data; - if (clkid < (enum clock_id)TEGRA_CLK_PLLS) { + if (clkid < (enum clock_id)TEGRA_CLK_PLLS) pll = get_pll(clkid); - } else { + else simple_pll = clock_get_simple_pll(clkid); - if (!simple_pll) { - debug("%s: Uknown simple PLL %d\n", __func__, clkid); - return 0; - } + + if (!simple_pll && !pll) { + log_err("Unknown PLL id %d\n", clkid); + return 0; } /* @@ -542,7 +542,8 @@ unsigned int __weak clk_m_get_rate(unsigned int parent_rate) unsigned clock_get_rate(enum clock_id clkid) { - struct clk_pll *pll; + struct clk_pll *pll = NULL; + struct clk_pll_simple *simple_pll = NULL; u32 base, divm; u64 parent_rate, rate; struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid]; @@ -554,10 +555,20 @@ unsigned clock_get_rate(enum clock_id clkid) if (clkid == CLOCK_ID_CLK_M) return clk_m_get_rate(parent_rate); - pll = get_pll(clkid); - if (!pll) + if (clkid < (enum clock_id)TEGRA_CLK_PLLS) + pll = get_pll(clkid); + else + simple_pll = clock_get_simple_pll(clkid); + + if (!simple_pll && !pll) { + log_err("Unknown PLL id %d\n", clkid); return 0; - base = readl(&pll->pll_base); + } + + if (pll) + base = readl(&pll->pll_base); + else + base = readl(&simple_pll->pll_base); rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask); divm = (base >> pllinfo->m_shift) & pllinfo->m_mask; @@ -599,12 +610,24 @@ unsigned clock_get_rate(enum clock_id clkid) int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) { u32 base_reg, misc_reg; - struct clk_pll *pll; + struct clk_pll *pll = NULL; + struct clk_pll_simple *simple_pll = NULL; struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid]; - pll = get_pll(clkid); + if (clkid < (enum clock_id)TEGRA_CLK_PLLS) + pll = get_pll(clkid); + else + simple_pll = clock_get_simple_pll(clkid); + + if (!simple_pll && !pll) { + log_err("Unknown PLL id %d\n", clkid); + return 0; + } - base_reg = readl(&pll->pll_base); + if (pll) + base_reg = readl(&pll->pll_base); + else + base_reg = readl(&simple_pll->pll_base); /* Set BYPASS, m, n and p to PLL_BASE */ base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift); @@ -631,21 +654,37 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) } base_reg |= PLL_BYPASS_MASK; - writel(base_reg, &pll->pll_base); + if (pll) + writel(base_reg, &pll->pll_base); + else + writel(base_reg, &simple_pll->pll_base); /* Set cpcon (KCP) to PLL_MISC */ - misc_reg = readl(&pll->pll_misc); + if (pll) + misc_reg = readl(&pll->pll_misc); + else + misc_reg = readl(&simple_pll->pll_misc); + misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift); misc_reg |= cpcon << pllinfo->kcp_shift; - writel(misc_reg, &pll->pll_misc); + if (pll) + writel(misc_reg, &pll->pll_misc); + else + writel(misc_reg, &simple_pll->pll_misc); /* Enable PLL */ base_reg |= PLL_ENABLE_MASK; - writel(base_reg, &pll->pll_base); + if (pll) + writel(base_reg, &pll->pll_base); + else + writel(base_reg, &simple_pll->pll_base); /* Disable BYPASS */ base_reg &= ~PLL_BYPASS_MASK; - writel(base_reg, &pll->pll_base); + if (pll) + writel(base_reg, &pll->pll_base); + else + writel(base_reg, &simple_pll->pll_base); return 0; } diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index 8ad71f590f..9a8c10e3d6 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -768,6 +768,21 @@ void arch_timer_init(void) debug("%s: TSC CNTCR = 0x%08X\n", __func__, val); } +struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + + switch (clkid) { + case CLOCK_ID_XCPU: + case CLOCK_ID_EPCI: + case CLOCK_ID_SFROM32KHZ: + return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + default: + return NULL; + } +} + struct periph_clk_init periph_clk_init_table[] = { { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, { PERIPH_ID_SBC2, CLOCK_ID_PERIPH }, diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index ca9549a318..ed8b6d9638 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -1189,10 +1189,16 @@ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - if (clkid == CLOCK_ID_DP) + switch (clkid) { + case CLOCK_ID_XCPU: + case CLOCK_ID_EPCI: + case CLOCK_ID_SFROM32KHZ: + return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + case CLOCK_ID_DP: return &clkrst->plldp; - - return NULL; + default: + return NULL; + } } struct periph_clk_init periph_clk_init_table[] = { diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c index abd6e3917a..109b73bfbe 100644 --- a/arch/arm/mach-tegra/tegra20/clock.c +++ b/arch/arm/mach-tegra/tegra20/clock.c @@ -792,6 +792,21 @@ int tegra_plle_enable(void) return 0; } +struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + + switch (clkid) { + case CLOCK_ID_XCPU: + case CLOCK_ID_EPCI: + case CLOCK_ID_SFROM32KHZ: + return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + default: + return NULL; + } +} + struct periph_clk_init periph_clk_init_table[] = { { PERIPH_ID_SPI1, CLOCK_ID_PERIPH }, { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index 900537afbe..74817e0440 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -1266,6 +1266,21 @@ int tegra_plle_enable(void) return 0; } +struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + + switch (clkid) { + case CLOCK_ID_XCPU: + case CLOCK_ID_EPCI: + case CLOCK_ID_SFROM32KHZ: + return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + default: + return NULL; + } +} + struct periph_clk_init periph_clk_init_table[] = { { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, { PERIPH_ID_SBC2, CLOCK_ID_PERIPH }, diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c index 698c7ab956..7bbe70921f 100644 --- a/arch/arm/mach-tegra/tegra30/clock.c +++ b/arch/arm/mach-tegra/tegra30/clock.c @@ -871,6 +871,21 @@ int tegra_plle_enable(void) return 0; } +struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + + switch (clkid) { + case CLOCK_ID_XCPU: + case CLOCK_ID_EPCI: + case CLOCK_ID_SFROM32KHZ: + return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + default: + return NULL; + } +} + struct periph_clk_init periph_clk_init_table[] = { { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, { PERIPH_ID_SBC2, CLOCK_ID_PERIPH }, -- 2.39.5