From 009fe1bac96889bd5f10f8d7a3edf4f1ba125ff3 Mon Sep 17 00:00:00 2001
From: Jagan Teki <jagan@amarulasolutions.com>
Date: Tue, 16 Jul 2019 17:27:14 +0530
Subject: [PATCH] ram: rk3399: Configure PHY_898, PHY_919 for lpddr4
PHY_898, PHY_919 would require to configure PHY LP4 boot
pll control and ca for lpddr4.
So, configure the same in pctl_cfg for LPDDR4.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 8b2c6b3cdb..aaf786a03e 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -574,6 +574,11 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
writel(params->phy_regs.denali_phy[911], &denali_phy[911]);
writel(params->phy_regs.denali_phy[912], &denali_phy[912]);
+ if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
+ writel(params->phy_regs.denali_phy[898], &denali_phy[898]);
+ writel(params->phy_regs.denali_phy[919], &denali_phy[919]);
+ }
+
dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) &
PWRUP_SREFRESH_EXIT;
clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
--
2.39.5