Patrick Delaunay [Fri, 11 Dec 2020 14:32:30 +0000 (15:32 +0100)]
configs: stm32mp1: activate OF_LIVE for DT live support
Activate the live DT to reduce the DT parsing time.
For example the boot time is reduced by 200ms on STM32MP157C-EV1 board
for stm32mp15_basic_defconfig (boot with SPL) or
stm32mp15_trusted_defconfig (boot with TF-A).
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Marek Vasut [Tue, 1 Dec 2020 10:34:48 +0000 (11:34 +0100)]
ARM: dts: stm32: Switch to MCO2 for PHY 50 MHz clock
The LAN8710i PHY currently uses 50 MHz clock direct from PLL4P.
To permit PLL4P to run at faster frequency, use MCO2 as a divider.
The PLL4P runs at 100 MHz, supplies MCO2 which divides it by 2 to
50MHz, and supplies the PHY with 50 MHz via pin PG2. The feedback
clock are fed back in via pin PA1.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ia9bf7119785d49b633a3ae761c3dc4a30b92628a
Michal Simek [Mon, 5 Oct 2020 09:37:00 +0000 (11:37 +0200)]
ARM: stm32: Use firmware property instead of loadables
There shouldn't be a need to use loadables propertyn because u-boot can be
pointed by firmware property. This change should also speedup boot process
because loadables property is list of strings which code is going through.
On the other hand firmware can just point to one image.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Fri, 16 Oct 2020 07:28:59 +0000 (09:28 +0200)]
board: stm32pm1: update USB-C power detection algorithm on DK boards
USB-C power supply which are Power Delivery compliant (USB-PD) are able
to provide different voltage/current (for example 5V/3A 9V/3A 12V/2.25A...)
In this case, the power supply need to negotiate the voltage/current to
use with the device using CC1/CC2 USB-C signals.
If this negotiation occurs during ADC measurement (done also on CC1/CC2
USB-C signals) some ADC acquisition can be corrupted which cause wrong
power supply current detection.
To avoid this, the power supply current detection algorithm is updated
as following:
- perform an ADC measurement, if a 3A current is detected, continue the
boot process.
- else, wait 20ms (max tPDDebounce duration) to ensure that USB-PD
negotiation is done and perform another ADC measurement.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
mmc: stm32_sdmmc2: migrate trace to dev and log macro
Define LOG_CATEGORY, use dev_ macro when it is possible.
Remove the "%s:" __func__ header as it is managed by dev macro
(dev->name is displayed) or log macro (CONFIG_LOGF_FUNC).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Tom Rini [Tue, 12 Jan 2021 14:32:48 +0000 (09:32 -0500)]
Merge tag 'ti-v2021.04-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- DM support for OMAP PWM backlight
- USB host mode support for AM654
- Minor SPI fixes
- Add support k2g ice board with 1GHz silicon
- Fix GTC programming for K3 devices
Tom Rini [Tue, 12 Jan 2021 14:32:20 +0000 (09:32 -0500)]
Merge tag 'u-boot-atmel-2021.04-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
First set of u-boot-atmel features for 2021.04 cycle
This feature set includes the new board SAMA7G5 EK, the new evaluation
kit for Microchip AT91 SAMA7G5 SoC . The current board support includes
two configurations for booting from eMMC (SDMMC0), SD-Card (SDMMC1), and
support for two Ethernet interfaces.
Nishanth Menon [Wed, 6 Jan 2021 19:20:32 +0000 (13:20 -0600)]
remoteproc: ti_k3_arm64: Program CNTFID0 register in GTC
ARMv8's generic timer[1] picks up it's graycode from GTC. However,
the frequency of the GTC is supposed to be programmed in CNTFID0[2]
register prior to enabling the GTC in CNTCR[3] register.
In K3 architecture, GTC provides a central time to many parts of the
SoC including graycode to the generic timer in the ARMv8 subsystem.
However, due to the central nature and the need to enable the counter
early in the boot process, the R5 based u-boot enables GTC and
programs it's frequency based on central needs of the system. This
may not be a constant 200MHz based on the system. The bootloader is
supposed to program the FID0 register with the correct frequency it
has sourced for GTC from the central system controller OR from PLLs
as appropriate, and TF-A is supposed[4] to use that as the frequency for
it's local timer.
Currently we are programming just the CNTCR[3] register to enable the
GTC, however we dont let TF-A know the frequency that GTC is actually
running at. A mismatch in programmed frequency and what we program for
generic timer will, as we can imagine, all kind of weird mayhem.
So, program the CNTFID0 register with the clock frequency. Note:
assigned-clock-rates should have set the clock frequency, so the only
operation we need to explicitly do is to retrieve the frequency and
program it in FID0 register.
Since the valid in K3 for GTC clock frequencies are < U32_MAX, we can
just cast the ulong and continue.
Pali Rohár [Sun, 29 Nov 2020 16:15:05 +0000 (17:15 +0100)]
Nokia RX-51: Add test for U-Boot serial console
This patch adds a new test which checks that U-Boot for Nokia RX-51 running
in qemu can print test line to serial console and also checks that test
line appeared on qemu serial console.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Pavel Machek <pavel@ucw.cz>
Dario Binacchi [Tue, 29 Dec 2020 23:16:30 +0000 (00:16 +0100)]
video: omap: split the legacy code from the DM code
The schedule for deprecating the features of the pre-driver-model puts
2019.17 as the deadline for the video subsystem. Furthermore, the latest
patches applied to the am335x-fb.c module have decreased the amount of
code shared with the pre-driver-model implementation. Splitting the two
implementations into two modules improves the readability of the code
and will make it easier to drop the pre-driver-model code.
I have not created a header file with the data structures and the
constants for accessing the LCD controller registers, but I preferred to
keep them inside the two c modules. This is a code replication until the
pre-driver-model version is dropped.
Dario Binacchi [Tue, 29 Dec 2020 23:16:29 +0000 (00:16 +0100)]
video: omap: set LCD clock rate through DM API
The patch configures the display DPLL using the functions provided by
the driver model API for the clock. The device tree contains everything
needed to get the DPLL clock. The round rate function developed for
calculating the DPLL multiplier and divisor and the platform routines
for accessing the DPLL registers are removed from the LCD driver code
because they are implemented inside the DPLL clock driver.
Dario Binacchi [Tue, 29 Dec 2020 23:16:27 +0000 (00:16 +0100)]
video: omap: add panel driver
The previous version of am335x-fb.c contained the functionalities of two
drivers that this patch has split. It was a video type driver that used
the same registration compatible string that now registers a panel type
driver. The proof of this is that two compatible strings were referred
to within the same driver.
There are now two drivers, each with its own compatible string,
functions and API.
Furthermore, the panel driver, in addition to decoding the display
timings, is now also able to manage the backlight.
Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
Dario Binacchi [Tue, 29 Dec 2020 23:16:25 +0000 (00:16 +0100)]
bus: ti: am33xx: add pwm subsystem driver
The TI PWMSS driver is a simple bus driver for providing clock and power
management for the PWM peripherals on TI AM33xx SoCs, namely eCAP,
eHRPWM and eQEP.
For DT binding details see Linux doc:
- Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt
Dario Binacchi [Tue, 29 Dec 2020 23:16:24 +0000 (00:16 +0100)]
pwm: ti: am33xx: add enhanced pwm driver
Enhanced high resolution PWM module (EHRPWM) hardware can be used to
generate PWM output over 2 channels. This commit adds PWM driver support
for EHRPWM device present on AM33XX SOC.
The code is based on the drivers/pwm/pwm-tiehrpwm.c driver of the Linux
kernel version 5.9-rc7.
For DT binding details see:
- Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
Dario Binacchi [Tue, 29 Dec 2020 23:16:21 +0000 (00:16 +0100)]
fdt: translate address if #size-cells = <0>
The __of_translate_address routine translates an address from the
device tree into a CPU physical address. A note in the description of
the routine explains that the crossing of any level with
since inherited from IBM. This does not happen for Texas Instruments, or
at least for the beaglebone device tree. Without this patch, in fact,
the translation into physical addresses of the registers contained in the
am33xx-clocks.dtsi nodes would not be possible. They all have a parent
with #size-cells = <0>.
The CONFIG_OF_TRANSLATE_ZERO_SIZE_CELLS symbol makes translation
possible even in the case of crossing levels with #size-cells = <0>.
The patch acts conservatively on address translation, except for
removing a check within the of_translate_one function in the
drivers/core/of_addr.c file:
There are two reasons:
1 The function of_empty_ranges_quirk always returns false, invalidating
the following if statement in case of null ranges. Therefore one of
the two checks is useless.
2 The implementation of the of_translate_one function found in the
common/fdt_support.c file has removed this check while keeping the one
about the 1:1 translation.
The patch adds a test and modifies a check for the correctness of an
address in the case of enabling translation also for zero size cells.
The added test checks translations of addresses generated by nodes of
a device tree similar to those you can find in the files am33xx.dtsi
and am33xx-clocks.dtsi for which the patch was created.
The patch was also tested on a beaglebone black board. The addresses
generated for the registers of the loaded drivers are those specified
by the AM335x reference manual.
Dario Binacchi [Tue, 29 Dec 2020 23:06:39 +0000 (00:06 +0100)]
clk: ti: add support for clkctrl clocks
Until now the clkctrl clocks have been enabled/disabled through platform
routines. Thanks to this patch they can be enabled and configured directly
by the probed devices that need to use them.
For DT binding details see Linux doc:
- Documentation/devicetree/bindings/clock/ti-clkctrl.txt
Dario Binacchi [Tue, 29 Dec 2020 23:06:38 +0000 (00:06 +0100)]
ti: am33xx: fix do_enable_clocks() to accept NULL parameters
Up till this commit passing NULL as input parameter was allowed, but not
handled properly. When a NULL parameter was passed to the function a data
abort was raised.
Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
Dario Binacchi [Tue, 29 Dec 2020 23:06:36 +0000 (00:06 +0100)]
clk: ti: add gate clock driver
The patch adds support for TI gate clock binding. The code is based on
the drivers/clk/ti/gate.c driver of the Linux kernel version 5.9-rc7.
For DT binding details see:
- Documentation/devicetree/bindings/clock/ti/gate.txt
Dario Binacchi [Tue, 29 Dec 2020 23:06:35 +0000 (00:06 +0100)]
clk: ti: add divider clock driver
The patch adds support for TI divider clock binding. The driver uses
routines provided by the common clock framework (ccf).
The code is based on the drivers/clk/ti/divider.c driver of the Linux
kernel version 5.9-rc7.
For DT binding details see:
- Documentation/devicetree/bindings/clock/ti/divider.txt
Dario Binacchi [Tue, 29 Dec 2020 23:06:34 +0000 (00:06 +0100)]
clk: ti: am33xx: add DPLL clock drivers
The digital phase-locked loop (DPLL) provides all interface clocks and
functional clocks to the processor of the AM33xx device. The AM33xx
device integrates five different DPLLs:
* Core DPLL
* Per DPLL
* LCD DPLL
* DDR DPLL
* MPU DPLL
The patch adds support for the compatible strings:
* "ti,am3-dpll-core-clock"
* "ti,am3-dpll-no-gate-clock"
* "ti,am3-dpll-no-gate-j-type-clock"
* "ti,am3-dpll-x2-clock"
The code is loosely based on the drivers/clk/ti/dpll.c drivers of the
Linux kernel version 5.9-rc7.
For DT binding details see:
- Documentation/devicetree/bindings/clock/ti/dpll.txt
Dario Binacchi [Tue, 29 Dec 2020 23:06:32 +0000 (00:06 +0100)]
clk: ti: add mux clock driver
The driver manages a register-mapped multiplexer with multiple input
clock signals or parents, one of which can be selected as output. It
uses routines provided by the common clock framework (ccf).
The code is based on the drivers/clk/ti/mux.c driver of the Linux
kernel version 5.9-rc7.
For DT binding details see:
- Documentation/devicetree/bindings/clock/ti/mux.txt
Dario Binacchi [Tue, 29 Dec 2020 23:06:31 +0000 (00:06 +0100)]
clk: add clk_round_rate()
It returns the rate which will be set if you ask clk_set_rate() to set
that rate. It provides a way to query exactly what rate you'll get if
you call clk_set_rate() with that same argument.
So essentially, clk_round_rate() and clk_set_rate() are equivalent
except the former does not modify the clock hardware in any way.
Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
Dario Binacchi [Tue, 29 Dec 2020 23:06:30 +0000 (00:06 +0100)]
arm: dts: sync am33xx with Linux 5.9-rc7
There have been several changes to the am33xx.dtsi, so this patch
re-syncs it with Linux.
Let's add proper interconnect hierarchy for l4 interconnect instances
with the related ti-sysc interconnect module data as documented in
Documentation/devicetree/bindings/bus/ti-sysc.txt of the Linux kernel.
With l4 interconnect hierarchy and ti-sysc interconnect target module
data in place, we can simply move all the related child devices to their
proper location and enable probing using ti-sysc.
The am33xx-clock.dtsi file is the same as that of the Linux kernel,
except for the reg property of the node l4-wkup-clkctrl@0.
As for the am33xx.dtsi file, all the devices with drivers not yet
implemented and those I was able to test with this patch have been moved
to am33xx-l4.dtsi. In case of any regressions, problem devices can be
reverted by moving them back and removing the related interconnect
target module node.
We can handle the sysc interconnect target module in a generic way for
many TI SoCs. Initially let's just enable domain clocks before the
children are probed.
The code is loosely based on the drivers/bus/ti-sysc.c of the Linux
kernel version 5.9-rc7.
For DT binding details see:
- Documentation/devicetree/bindings/bus/ti-sysc.txt
Dario Binacchi [Tue, 29 Dec 2020 23:06:28 +0000 (00:06 +0100)]
dt-bindings: bus: ti-sysc: resync with Linux 5.9-rc7
Add support for PRUSS SYSC type:
The PRUSS module has a SYSCFG which is unique. The SYSCFG has two
additional unique fields called STANDBY_INIT and SUB_MWAIT in addition
to regular IDLE_MODE and STANDBY_MODE fields. Add the bindings for this
new sysc type.
Add support for MCAN on dra76x:
The dra76x MCAN generic interconnect module has a its own format for the
bits in the control registers.
Felix Brack [Fri, 18 Dec 2020 08:03:50 +0000 (09:03 +0100)]
arm:pdu001: Use pseudo partition UUID for LINUX kernel boot paramter root
As more and more LINUX drivers are modified to use asynchronous probing
instead of synchronous probing, relying on device names being equal in
U-Boot and LINUX is not possible anymore. This is also true for block
device names like mmc0, mmc1 ect.
With LINUX kernel commit a1a4891 the probing type for the sdhci-omap
driver has been set to asynchronous mode too (probe_type is now
PROBE_PREFER_ASYNCHRONOUS).
In the case of the PDU001 board this results in the devices mmc0 and
mmc1 being swapped between U-Boot and LINUX. Device mmc0 in U-Boot
becomes mmc1 in LINUX an vice versa. Hence using device name identifiers
with LINUX kernel parameter root does not work anymore.
This patch changes the LINUX kernel boot parameter root to use the
pseudo (since we use MBR not GPT) partition UUID to locate the partition
hosting the root file system.
McSPI IP provides per CS specific speed and mode selection. Therefore it
is possible to apply these settings only after CS is known. But
set_speed and set_mode can be called without bus being claimed, this
would lead driver to set up wrong CS (or previously used CS).
Fix this by apply set_speed and set_mode only if bus is already claimed.
Ovidiu Panait [Sat, 28 Nov 2020 08:11:28 +0000 (10:11 +0200)]
spi: ti_qspi: Fix "spi-max-frequency" error path in ti_qspi_ofdata_to_platdata
struct ti_qspi_priv->max_hz is declared as unsigned int, so the following
error path check will always be false, even when "spi-max-frequency"
property is invalid/missing:
priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
if (priv->max_hz < 0) {
...
}
Replace the fdtdec call with dev_read_u32_default() and use 0 as the
default value. Error out if max_hz is zero.
Tomas Novotny [Wed, 25 Nov 2020 17:42:16 +0000 (18:42 +0100)]
gpio: tca642x: fix input subcommand for gpio banks > 0
The value of input pin for bank > 0 is always 0 for input subcommand.
The reason is that gpio_bank variable is computed only for invert and
output subcommands (it depends on number of arguments). The default
value of zero causes to shift the mask away for banks > 0.
Please note that info subcommand works as expected, because the input
pin values are accessed differently.
Fixes: 61c1775f16ed ("gpio: tca642x: Add the tca642x gpio expander driver") Cc: Dan Murphy <dmurphy@ti.com> Signed-off-by: Tomas Novotny <tomas@novotny.cz>
configs: am65x_evm: Define the maximum file size for DFU
In include/dfu.h, if CONFIG_SYS_DFU_MAX_FILE_SIZE is not defined then it is
defined as CONFIG_SYS_DFU_DATA_BUF_SIZE. This is 128 KiB for a53 core and
20 KiB for r5 core. If a larger file is transferred using dfu then it
fails.
CONFIG_SYS_DFU_DATA_BUF_SIZE can not be increased as there is not enough
heap memory to be allocated for the buffer in case of R5 spl.
Fix this by defining CONFIG_SYS_DFU_MAX_FILE_SIZE as the default
CONFIG_SYS_DFU_DATA_BUF_SIZE value.
arm: dts: am654-base-board-uboot: Add aliases for USB subsystems
The sequence number assigned for USB subsystem in a uclass is dependent on
the order of occurrence in the device tree. If the dr_mode of USB3SS0
controller is varied then the sequence number of USB3SS1 controller also
changes. If aliases are added then sequence numbers are assigned using the
alias number. This makes the sequence number of USB3SS1 controller
independent of USB3SS0 controller's dr_mode.
Therefore, add aliases to fix the sequence number assigned to the USB
subsystems.
board: ti: am65x: Set SERDES0 mux to PCIe to use USB 2.0 interface
It has been observed that setting SERDES0 lane mux to USB prevents USB 2.0
operation on USB0. Setting SERDES0 lane mux to non-USB when USB0 is used in
USB 2.0 only mode solves this issue. However, for USB3.0+2.0 operation this
issue is not present.
Implement this workaround by writing 1 to LANE_FUNC_SEL field in
CTRLMMR_SERDES0_CTRL register.
Tom Rini [Tue, 12 Jan 2021 02:23:59 +0000 (21:23 -0500)]
Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi
- Pinecube board support
- 64-bit FEL support
- mkimage support for eGON images (superseding mksunxiboot)
- Bluetooth BD address generation
- some fixes
Andre Heider [Fri, 1 Oct 2021 18:29:00 +0000 (19:29 +0100)]
sunxi: board: add a config option to fixup a Bluetooth address
Some Bluetooth controllers, like the BCM4345C5 of the Orange Pi 3,
ship with the controller default address.
Add a config option to fix it up so it can function properly.
Signed-off-by: Andre Heider <a.heider@gmail.com> Tested-by: Ondrej Jirman <megous@megous.com> Acked-by: Maxime Ripard <mripard@kernel.org>
[rebased] Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Jernej Skrabec [Thu, 12 Mar 2020 17:46:00 +0000 (17:46 +0000)]
sunxi: dram: h6: Improve DDR3 config detection
It turns out that in rare cases, current analytical approach to detect
correct DRAM bus width and rank on H6 doesn't work. On some TV boxes
with DDR3, incorrect DRAM configuration triggers write leveling error
which immediately stops initialization process. Exact reason why this
error appears isn't known. However, if correct configuration is used,
initalization works without problem.
In order to fix this issue, simply try another configuration when any
kind of error appears during initialization, not just those related to
rank and bus width.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Tested-by: Thomas Graichen <thomas.graichen@googlemail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andy Shevchenko [Tue, 8 Dec 2020 15:45:31 +0000 (17:45 +0200)]
sunxi: board: Move USB ethernet initialization to board_late_init()
For the sake of consistency (*) and order of initialization, i.e.
after we have got the ethernet address, interrupt and timer initialized,
try to initialize USB ethernet gadget.
*) for example, zynqmp uses same order.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Tue, 23 Aug 2016 21:19:30 +0000 (22:19 +0100)]
sunxi: Add arm64 FEL support
So far we did not support the BootROM based FEL USB debug mode on the
64-bit builds for Allwinner SoCs: The BootROM is using AArch32, but the
SPL runs in AArch64.
Returning back to AArch32 was not working as expected, since the RMR
reset into 32-bit mode always starts execution in the BootROM, but not
in the FEL routine.
After some debug and research and with help via IRC, the CPU hotplug
mechanism emerged as a solution: If a certain R_CPUCFG register contains
some magic, the BootROM will immediately branch to an address stored in
some other register. This works well for our purposes.
Enable the FEL feature by providing early AArch32 code to first save the
FEL state, *before* initially entering AArch64.
If we eventually determine that we should return to FEL, we reset back
into AArch32, and use the CPU hotplug mechanism to run some small
AArch32 code snippet that restores the initially saved FEL state.
That allows the normal AArch64 SPL build to be loaded via the sunxi-fel
tool, with it returning into FEL mode, so that other payloads can be
transferred via FEL as well.
Tested on A64, H5 and H6.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Priit Laes <plaes@plaes.org> (on Olimex A64-Olinuxino)
Andre Przywara [Thu, 20 Dec 2018 15:41:34 +0000 (15:41 +0000)]
sunxi: Use mkimage for SPL boot image generation
Switch the SPL boot image generation from using mksunxiboot to the new
sunxi_egon format of mkimage.
Verified to create identical results for all 152 Allwinner boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Samuel Holland <samuel@sholland.org>
Andre Przywara [Thu, 20 Dec 2018 01:15:18 +0000 (01:15 +0000)]
tools: mkimage: Add Allwinner eGON support
So far we used the separate mksunxiboot tool for generating a bootable
image for Allwinner SPLs, probably just for historical reasons.
Use the mkimage framework to generate a so called eGON image the
Allwinner BROM expects.
The new image type is called "sunxi_egon", to differentiate it
from the (still to be implemented) secure boot TOC0 image.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Andre Przywara [Tue, 17 Nov 2020 23:36:05 +0000 (23:36 +0000)]
sunxi: Factor out eGON BROM header description
To be able to easily share the Allwinner eGON BROM header structure
between the tools and the SPL code, move the struct definition into a
separate header file.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Samuel Holland <samuel@sholland.org>
Icenowy Zheng [Wed, 18 Nov 2020 10:27:00 +0000 (10:27 +0000)]
sunxi: add PineCube board
PineCube is an IP camera development kit released by Pine64.
It comes with the following compoents:
- A mainboard with Sochip S3 SoC, a 16MByte SPI Flash, AXP209 PMIC,
a power-only microUSB connector, a USB Type-A connector, a 10/100Mbps
Ethernet port and FPC connectors for camera and daughter board.
- An OV5640-based camera module which is connected to the parallel CSI
bus of the mainboard.
- A daughterboard with several buttons, a SD slot, some IR LEDs, a
microphone and a speaker connector.
As the device tree is synchronized in a previous commit, just add it to
Makefile, create a new MAINTAINER item and provide a defconfig.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Lukasz Majewski [Sat, 26 Dec 2020 00:09:02 +0000 (01:09 +0100)]
xea: config: Disable CONFIG_SPL_OF_PLATDATA_PARENT on XEA (imx28)
On the XEA board (imx28) one needs in the SPL support for GPIO, MMC and
SPI. Two last ones are necessary for booting the device. The GPIO support
allows deciding which medium will be used. For example the GPIO DTS node
(gpio@0 at imx28.dtsi) has pinctrl parent (pinctrl@80018000) for which we
don't need driver asigned for correct operation.
In the spl/dts/dt-platdata.c the gpio@0 has index 4 and its parent -
pinctrl@80018000 has index 5.
In the bind_drivers_pass() function (at drivers/core/lists.c) call to
device_bind_by_name() for `fsl_imx23_pinctrl` returns -2, which is
expected.
With current setup - when the SPL_OF_PLATDATA_PARENT=y
The gpio@0 node with index 4 is skipped as its parent with 5 is not yet
bound. It cannot be as we don't need and provide the driver for it.
As a result the gpio@0 is never bound and we end up with bricked board in
the SPL stage.
When CONFIG_SPL_OF_PLATDATA_PARENT is NOT set, all entries from
spl/dts/dt-platdata.c are scanned in ascending index order, so gpio@0 is
properly initialized. For `fsl_imx_pinctrl` we simply check 10 times if
the driver for is available (which is not) and exit.
As a result the GPIOs are initialized and can be used in early SPL stage.
This commit fixes XEA regression introduced with e41651fffda7da55f6.
Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Lukasz Majewski [Sat, 26 Dec 2020 00:09:01 +0000 (01:09 +0100)]
xea: config: Use CONFIG_PREBOOT from Kconfig
The usage of the preboot feature is now controlled via a separate Kconfig
option - namely CONFIG_USE_PREBOOT.
It must be enabled for preboot code executing commands now defined in
CONFIG_PREBOOT (also moved to the Kconfig).
After defining both CONFIG_USE_PREBOOT and CONFIG_PREBOOT in
imx28_xea_defconfig the define of CONFIG_PREBOOT shall be removed from
xea.h as it is redundant.
Hugh Cole-Baker [Sun, 22 Nov 2020 13:03:44 +0000 (13:03 +0000)]
rockchip: pinebook-pro: default to SPI bus 1 for SPI-flash
SPI flash on this machine is located on bus 1, default to using bus 1
for SPI flash and stop aliasing it to bus 0.
Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com> Suggested-by: Simon Glass <sjg@chromium.org> Fixes: c4cea2bb ("rockchip: Enable building a SPI ROM image on bob")
Nicolas Ferre [Fri, 30 Oct 2020 17:33:14 +0000 (18:33 +0100)]
ARM: dts: sama7g5ek: fix TXC pin configuration
TXC line is directly connected from the SoC to the KSZ9131 PHY. There
is a transient state on this signal, before configuring it to RGMII,
which leads to packet transmit being blocked.
Keeping a pull-up when muxing this pin as function A (G0_TXCK) fixes
the issue.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
projects / u-boot.git / log
