Jonas Karlman [Thu, 25 Jul 2024 09:46:03 +0000 (09:46 +0000)]
rockchip: px30/rk3326: Use soc dtsi files from dts/upstream
The commit f087f7fd277d ("rockchip: px30/rk3326: migrate to
OF_UPSTREAM") migrated px30/rk3326 boards to use OF_UPSTREAM, however
the soc dtsi and dt-bindings files remained.
Remove the remaining px30/rk3326 soc dtsi and dt-bindings to ensure the
files from dts/upstream is used.
The gpio-ranges props is moved to u-boot.dtsi files and a ethernet0
alias is added to px30-firefly, they are missing in the dts/upstream
files. No changes are expected with this.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Jonas Karlman [Wed, 24 Jul 2024 06:58:15 +0000 (06:58 +0000)]
rockchip: io-domain: Add support for RK3308
Port the RK3308 part of the Rockchip IO Domain driver from linux.
This differs from linux version in that vccio3 iodomain bit is enabled
in the write ops instead of in an init ops as in linux, this way we can
avoid keeping a full state of all supply that have been configured.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Wed, 24 Jul 2024 06:55:36 +0000 (06:55 +0000)]
mmc: rockchip_dw_mmc: Allow 4-bit mode when 8-bit mode is supported
Hosts capable of 8-bit can also do 4 bits, fix use of 4-bit mode when
8-bit mode is supported.
This fixes use of 1-bit mode with SD NAND on ROCK Pi S using the DT in
v6.11-rc1 that chage to use 8-bit bus to also support eMMC. With this
4-bit mode is used with SD NAND and 8-bit mode with eMMC, same as in
Linux kernel.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
phy: rockchip: naneng-combphy: Introduce PHY-IDs to fix RK3588 muxing
Fix multiplex configuration for PCIe1L0 and PCIe1L1 in PCIESEL_CON for
RK3588 to correctly select between Combo PHYs and PCIe3 PHY.
Currently, the code incorrectly muxes both ports to Combo PHYs,
interfering with PCIe3 PHY settings.
Introduce PHY identifiers to identify the correct Combo PHY and set
the necessary bits accordingly.
This fix is adapted from the upstream Linux commit by Sebastian Reichel: d16d4002fea6 ("phy: rockchip: naneng-combphy: Fix mux on rk3588")
Fixes: b37260bca1aa ("phy: rockchip: naneng-combphy: Use signal from comb PHY on RK3588") Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Sebastian Kropatsch <seb-dev@mail.de>
Tom Rini [Fri, 9 Aug 2024 00:37:11 +0000 (18:37 -0600)]
Merge patch series "Low Power Mode: Package TIFS Stub in BeaglePlay"
Dhruva Gole <d-gole@ti.com> says:
This series aims to add documentation around the boot flow and tispl
packaging details regarding the TIFS Stub. While at it, also refactors the
k3 common docs to add more labels to provide more granularity on how we
include chunks from common docs into SoC specific docs.
This series also includes the binman related changes required to package
TIFS Stub to support Low Power Modes on BeaglePlay and phycore-am625 SOM.
Dhruva Gole [Mon, 5 Aug 2024 14:29:37 +0000 (19:59 +0530)]
arm: dts: phycore-am62x: Package TIFS Stub
Add support for packaging the TIFS Stub as it's required for basic Low
Power Modes like Deep Sleep.
The reason it is packaged using binman and not inherently as part of the
DM firmware is because for HS devices, customer owns the customer key
and only customer has access to it.
DM is release by TI, Since TI doesn't have access to the customer key it
cannot have a component that is signed by customer key.
Hence, it's left as part of binman to be signed and packaged.
While at it, also make sure it's documented in phycore-am62x
Dhruva Gole [Mon, 5 Aug 2024 14:29:36 +0000 (19:59 +0530)]
doc: beagle: am62x_beagleplay: Document the use of TIFS Stub
* Include the actual common documentation about the TIFS Stub and role
it plays to enable Low Power Modes in the platform.
* Add the AM62x boot flow to show at which point the TIFS Stub actually
gets loaded.
* Mention the TIFS Stub in the TISPL image format.
Dhruva Gole [Mon, 5 Aug 2024 14:29:35 +0000 (19:59 +0530)]
arm: dts: k3-am625-beagleplay: Package TIFS Stub
Add support for packaging the TIFS Stub as it's required for basic Low
Power Modes like Deep Sleep.
The reason it is packaged using binman and not inherently as part of the
DM firmware is because for HS devices, customer owns the customer key
and only customer has access to it.
DM is release by TI, Since TI doesn't have access to the customer key it
cannot have a component that is signed by customer key.
Hence, it's left as part of binman to be signed and packaged.
Dhruva Gole [Mon, 5 Aug 2024 14:29:34 +0000 (19:59 +0530)]
doc: ti: am62*: Mention TIFS Stub in img fmts and boot flow
Since AM62x, AM62P and AM62A all use similar boot flows and their low
power mode s/w ARCH is also similar in the way that they make use of the
TIFS Stub, update their documentation to show where TIFS Stub is.
Dhruva Gole [Mon, 5 Aug 2024 14:29:32 +0000 (19:59 +0530)]
doc: ti: k3: Add TIFS Stub documentation
* Add documentation to briefly explain the role of TIFS Stub in relevant
K3 SoC's.
* Shed light on why TIFS Stub isn't package with the DM firmware itself.
* Modify the platform docs wherever the TIFS Stub documentation applies.
* Also, refactor and add a few new labels to help split the firmware
documentation chunks. This will make it easier to include them one by
one wherever applicable
Tom Rini [Thu, 8 Aug 2024 13:59:47 +0000 (07:59 -0600)]
Merge tag 'u-boot-nand-20240808' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash
This series adds support for the UBI block device, which allows to read/write
data block by block. The series was tested by Alexey Romanov on SPI NAND.
The patches pass the pipeline CI:
https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/21933
UBI block is an virtual device, that runs on top
of the MTD layer. The blocks are UBI volumes.
Intended to be used in combination with other MTD
drivers.
Despite the fact that it, like mtdblock abstraction,
it used with UCLASS_MTD, they can be used together
on the system without conflicting. For example,
using bcb command:
# Trying to load bcb via mtdblock:
$ bcb load mtd 0 mtd_partition_name
# Trying to load bcb via UBI block:
$ bcb load ubi 1 ubi_volume_name
User always must attach UBI layer (for example, using
ubi_part()) before using UBI block device.
Tom Rini [Tue, 6 Aug 2024 15:36:46 +0000 (09:36 -0600)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
This updates the "old style" DTs to that of Linux v6.10, matching what
OF_UPSTREAM is at now. Hopefully we won't need to do this (manually)
anymore. Since this brings in the DT for a new board (Tanix TX1), also
add the defconfig for that, which has just been waiting for that sync.
There are three more fixes: two for the SPI clock setup, which avoids
too high frequencies in some cases, and one fix to avoid a build warning
with GCC 14 for the sunxi TOC0 part of the mkimage tool.
The gitlab CI passed, and I tested the SPI flash on the OrangePi Zero 3
and also booted that into Linux.
Michael Walle [Thu, 18 Jul 2024 20:42:53 +0000 (22:42 +0200)]
spi: sunxi: fix clock divider calculation for max frequency setting
If the maximum frequency is requested, we still fall into the CDR2
handling. But there the minimal divider is 2. For the sun6i and sun8i we
can do better with the CDR1 setting where the minimal divider is 1:
SPI_CLK = MOD_CLK / 2 ^ cdr with cdr = 0
Thus, handle the div = 1 case specially.
While at it, correct the comment above the calculation.
Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Michael Walle [Thu, 18 Jul 2024 20:42:52 +0000 (22:42 +0200)]
spi: sunxi: fix CDR2 calculation
The CDR2 divider calculation always yield a frequency greater than the
requested one. Use DIV_ROUND_UP() to keep the frequency equal or below
the requested one. This way, we can also drop the "if div > 0" check
because we know for a fact that div cannot be zero.
FWIW, this aligns the CDR2 calculation with the linux driver.
Suggested-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Mon, 25 Mar 2024 21:58:39 +0000 (21:58 +0000)]
sunxi: h616: add Tanix TX1 support
The Tanix TX1 is a tiny TV box, featuring the Allwinner H313 SoC with up
to 2GB of DRAM and 16GB of eMMC. There is no SD card or Ethernet port on
this small device, but it can be booted via the USB debug "FEL" mode.
The bootloader could then be written to the eMMC.
Add the defconfig for that board, and add the devicetree file to the
Makefile, for it to be built.
The DRAM parameters were taken from the vendor firmware on the eMMC.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Fri, 19 Apr 2024 16:59:52 +0000 (17:59 +0100)]
sunxi: dts: arm/arm64: update devicetree files from Linux-v6.10
Sync the devicetree files from the official Linux kernel tree, v6.10.
This is covering Allwinner SoCs with 32-bit and 64-bit ARM cores.
Besides mostly cosmectic changes, this adds cpufreq support to H616
boards, Nothing that U-Boot needs for itself, but helpful to pass on
to kernels. We also get the .dts files for the Tanix TX1 TV box and
three Anbernic handheld gaming devices.
As before, this omits the non-backwards compatible changes to the R_INTC
controller, to remain compatible with older kernels.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Seung-Woo Kim [Thu, 1 Aug 2024 01:01:00 +0000 (10:01 +0900)]
tools: imagetool: Remove unnecessary check from toc0_verify_cert_item()
C99 introduced the possibility to mark function parameters declared as
arrays with an extra keyword "static":
void foo(uint8_t digest[static SHA256_DIGEST_LENGTH]);
This requires the respective function argument to be at least as large
as specified. Passing in random pointers (like NULL) then becomes
undefined behaviour, and compilers warn about this.
Newer GCC compilers (starting with GCC 14) will also automatically mark
those parameters as "nonnull", and thus warn if a (redundant) NULL check
is done inside the function:
tools/sunxi_toc0.o tools/sunxi_toc0.c
tools/sunxi_toc0.c: In function 'toc0_verify_cert_item':
tools/sunxi_toc0.c:447:12: warning: 'nonnull' argument 'digest' compared to NULL [-Wnonnull-compare]
447 | if (digest && memcmp(&extension->digest, digest, SHA256_DIGEST_LENGTH)) {
| ^
Remove the unnecessary NULL check from toc0_verify_cert_item(), to avoid
the warning.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
[Andre: extend commit message] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tom Rini [Mon, 5 Aug 2024 18:15:44 +0000 (12:15 -0600)]
Merge patch series "Bug-fixes for a few boards"
Simon Glass <sjg@chromium.org> says:
This series includes fixes to get some rockchip and nvidia boards
working again. It also drops the broken Beaglebone Black config and
provides a devicetree fix for coral (x86).
Simon Glass [Thu, 1 Aug 2024 12:47:23 +0000 (06:47 -0600)]
rockchip: Avoid #ifdefs in RK3399 SPL
The code here is confusing due to large blocks which are #ifdefed out.
Add a function phase_sdram_init() which returns whether SDRAM init
should happen in the current phase, using that as needed to control the
code flow.
This increases code size by about 500 bytes in SPL when the cache is on,
since it must call the rather large rockchip_sdram_size() function.
Simon Glass [Wed, 31 Jul 2024 14:49:05 +0000 (08:49 -0600)]
fdt: Correct condition for bloblist existing
On some boards, the bloblist is created in SPL once SDRAM is ready. It
cannot be accessed until that point, so is not available early in SPL.
Add a condition to avoid a hang in this case.
This fixes a hang in chromebook_coral
Fixes: 70fe2385943 ("fdt: Allow the devicetree to come from a bloblist") Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Raymond Mao <raymond.mao@linaro.org>
Michal Simek [Tue, 30 Jul 2024 10:42:43 +0000 (12:42 +0200)]
arm64: zynqmp: Remove PM firmware checking
Having zynqmp firmware is actually only one valid configuration. In QEMU
case for example there is no PMU that's why this checking can't end up in
panic that's why code remove this code completely.
The correct operating mode for the fan is inversed (1). The
previous pwm driver implementation had a bug and the polarity
information was propagated incorrectly to the kernel. The normal (0)
polarity specified in the device tree was incorrectly clearing the
polarity bit in the counter control register. After the bug fix,
setting the polarity to inversed (1) in the device tree will clear
the polarity bit.
arm64: zynqmp: dts: Add rts delay property for rs485 mode on KD240
Add "rs485-rts-delay" property to uartps node with delay_rts_before_send
and delay_rts_after_send values as 10ms for rs485 mode on KD240.
10ms rts delay values have been chosen based on testing with rs485
temperature sensor (which is part of the kit) as safe minimum value
for reliable operation at a baud rate of 9600.
Michal Simek [Mon, 15 Jul 2024 14:38:30 +0000 (16:38 +0200)]
arm64: versal-net: Align node names with dt-schema
dt-schema is forcing some rules for node names that's why align them with
it. Labels are not changing that's why this change is not breaking any
other board specific DTSes.
xilinx: versal-net: Handle spi seq number based on boot device
Versal NET boards has QSPI and OSPI and default bus set to 0
is not working when system is booting out of OSPI which is
controller 1, as fixed aliases are set for all the boards
i.e., QSPI to 0 and OSPI to 1. Add controller autodetection
via spi_get_env_dev().
env_spi: support overriding spi dev from board code
This enables boards to choose where to/from the environment
should be saved/loaded. They can then for example support using
the same device (dynamically) from which the bootloader was
launched to load and save env data and do not have to
define CONFIG_ENV_SPI_BUS statically.
In my use case, the environment needs to be on the same device I
booted from. It can be the QSPI or OSPI device.
I therefore would override spi_get_env_dev in the board code,
read the bootmode registers to determine where we booted from
and return the corresponding device index.
config: Enable the config CONFIG_MMC_SPEED_MODE_SET
Enable setting speed mode using mmc dev commands.
The speed mode is provided as the last argument in these commands
(ex: mmc dev 0 0 10) and is indicated using the index from enum
bus_mode in include/mmc.h. A speed mode can be set if it is enabled
from device tree or from capabilities register
clk: zynqmp: Add set_rate support for display clocks
If "assigned-clock-rates" property is included in the
device tree, display driver probe is getting failed, as dp_video_ref
till dp_stc_ref clocks are missing from set rate function, adding
them to fix the probe failure.
Hou Zhiqiang [Thu, 1 Aug 2024 03:59:55 +0000 (11:59 +0800)]
cmd: cpu: add release subcommand
Add a new subcommand 'release' to bring up a core to run baremetal
and RTOS applications.
For example on i.MX8M Plus EVK, release the LAST core to run a RTOS
application, passing the sequence number of the CPU core to release,
here it is 3:
u-boot=> cpu list
0: cpu@0 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
1: cpu@1 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 30C
2: cpu@2 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
3: cpu@3 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
u-boot=> load mmc 1:2 c0000000 /hello_world.bin
66008 bytes read in 5 ms (12.6 MiB/s)
u-boot=> dcache flush; icache flush
u-boot=> cpu release 3 c0000000
Released CPU core (mpidr: 0x3) to address 0xc0000000
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Hou Zhiqiang [Thu, 1 Aug 2024 03:59:47 +0000 (11:59 +0800)]
cpu: add release_core callback
Add a new callback release_core to the cpu_ops, which is used to
release a CPU core to run baremetal or RTOS application on a SoC
with multiple CPU cores.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Hou Zhiqiang [Thu, 1 Aug 2024 03:59:46 +0000 (11:59 +0800)]
clk: imx8m: register ARM A53 core clock
Register ARM A53 core clock for i.MX 8M Mini, Nano and Plus, preparing
for enabling the 'cpu' command, which depends on this to print CPU core
frequency.
Instead of using the local imx7s-warp devicetree copies from U-Boot,
convert the imx7s-warp board to OF_UPSTREAM so that the upstream
kernel devicetree can be used instead.
Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Alexander Dahl [Fri, 3 May 2024 07:20:09 +0000 (09:20 +0200)]
clk: Revise help text for clk_get_parent_rate()
The function returns the rate of the parent clock, the previous text
made no sense at all.
Fixes: 4aa78300a025 ("dm: clk: Define clk_get_parent_rate() for clk operations") Signed-off-by: Alexander Dahl <ada@thorsis.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
Jan Kiszka [Sat, 9 Mar 2024 12:27:09 +0000 (13:27 +0100)]
clk: Fix error message in clk_get_bulk
Fix a logical inversion of the printed text.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
Tom Rini [Thu, 1 Aug 2024 21:32:54 +0000 (15:32 -0600)]
Merge patch series "clk: mediatek: add OPs to support OF_UPSTREAM"
Christian Marangi <ansuelsmth@gmail.com> says:
This series doesn't currently change anything and it does add all the
additional OPs to make support of OF_UPSTREAM.
While converting the mt7681/7686/7688/7623/7622 it was notice lots of
discrepancy between the downstream dtsi and the upstream one and the
clock ID between downstream clock ID and upstream clock ID.
Upstream reference clock by names and clock are handled by the
CCF (Common Clock Framework). The same can't be used here as we would
quickly reach the max space allocated before relocation.
The current mediatek clock driver reference all the parents and clocks
with offset from the clk ID related to the different tables.
Discrepancy between clock ID and the order in the clocks table cause
one clock referenced for another or even crash for trying to access
a clock at an offset that doesn't exist.
To handle this and permit use of OF_UPSTREAM, various measure and
changes are done to the mediatek clock driver to support it.
This series have all the generic clock changes. Once this is merged,
series for each SoC will came that will just change files in their
dedicated clock driver. This is to prevent massive patch and to
permit to split series, one for each SoC.
As said at the start, these changes doesn't cause regression and are
just expansion to the current API. Current behaviour is saved in every
possible way (aside from the first 2 patch that fixes latent bugs)
clk: mediatek: add support for GATEs for APMIXED OPs
Add support for GATEs for APMIXED OPs. It's possible that some APMIXED
have also gates on top of PLL. This is the case for mt7622. Add support
for this.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
clk: mediatek: implement MUX_FLAGS and MUX_MIXED_FLAGS macro
Some simple MUX might require flags to specify the parent source.
Implement MUX_FLAGS as a variant of the MUX macro that takes custom
flags as last arg.
Also implement MUX_MIXED_FLAGS for PARENT_MIXED implementation and
MUX_MIXED with no additional flags.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Upstream kernel linux might have a different clock ID order in their
<soc>-clk.h header. This is the case of some clock ID for mt7623 that
upstream use the shared header clk-mt7601.h
This header doesn't have a well distincted order and have factor or mux
in the middle of the CLK ID list. This is problematic with the mtk clock
driver that expect everything well organized in block and apply offset
to reference the clk in the different array.
To solve this problem, implement in the mtk_clk_tree an additional
option .id_offs_map, an array where each CLK ID can be remapped to what
the driver expect permitting to reorganize the clock following the
expected logic of fixed, factor, mux and gates.
Each clock function is updated to tranparently handle this by first
converting the clk ID to the remapped one.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
clk: mediatek: provide common clk init function for infrasys
Provide common clk init function for infrasys that defaults to topckgen
driver if clock-parent is not defined. This is the case for upstream
DTSI that doesn't provide this entry.
This is needed for infracfg driver that will make use of the unified
gates + muxes implementation.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
clk: mediatek: add support for gate clock to reference topckgen clock
Add support for gate clock get_rate to reference topckgen clock for
infracfg-ao implementation.
In infracfg-ao implementation topckgen is on second level of parent with
infracfg in the middle.
To correctly detect this, check the driver of the dev parent and use the
second level parent if it's not mtk_clk_topckgen.
Due to all the dependency, parent tree must be filled before a gate is
used, hence is safe to assume it will be there.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
clk: mediatek: add support for parent mux from different source for topckgen
As done for infracfg, also add support for parent mux from different
source for topckgen. This is needed as upstream linux doesn't use 1/1
factor and use directly the APMIXED clocks.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
clk: mediatek: add support for parent mux from different source
There is a current limitation where parents for a mux can be all declared
as they are from a common source. This is not true as there are some MUX
that can have parent from both infracfg or from topckgen.
To handle this, implement a new flag for the mux, CLK_PARENT_MIXED, and
a new entry for the mux parent_flags.
To use this, CLK_PARENT_MIXED must be used and parent_flags will be used
instead of the parent variable.
Entry in parent_flags are just a struct of ID and flags where it will be
defined where that parent comes from with the usage of
CLK_PARENT_INFRASYS or CLK_PARENT_TOPCKGEN.
This permits to have MUX with parents from infracfg or topckgen.
Notice that with CLK_PARENT_MIXED applied the CLK_BYPASS_XTAL is
ignored.
With CLK_PARENT_MIXED declare CLK_PARENT_XTAL for the relevant parent
instead.
Also alias for the CLK_PARENT macro are provided to better clear their
usage. CLK_PARENT_MIXED require these alias that describe the clk type
to be defined in the clk_tree flags to prevent clk ID clash from
different subsystem that may have equal clk ID.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Add support to clk_gate ops to reference the clk ID at an offset by
using the just introduced gates_offs value from the unified muxes +
gates implementation.
Gate clock that doesn't have gates_offs set won't be affected as the
offset will simply be 0 and won't be offset of any value.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
clk: mediatek: add support for gates in clk_tree for infrasys
Add support for gates in clk_tree for infrasys ops.
Infracfg clks can have a sum of gates and muxes, and current solution
handle this by duplicating the driver and split clks for mux and clks
for gates. Upstream linux kernel handle this differently and doesn't
have this distinction.
To be closer to the upstream kernel clock definition, implement
additional logic to have gates defined in the clk_tree and implement
variant for the infrasys ops to handle gates defined in the tree.
Similar to how it's done with factor and mux, we introduce gates_offs.
Upstream kernel follow the similar logic with all the ID defined as
FDIVS, MUXES and finally GATES.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
clk: mediatek: return XTAL rate for infrasys get_mux_rate
We currently return 0 if XTAL rate is requested in get_mux_rate. This
deviates from what is done in get_factor_rate and is totally wrong as it
can cause unwanted results (division by 0 crash)
For infrasys that makes use of CLK_XTAL, assume xtal_rate to be defined
in clk_tree and return the rate when BYPASS_XTAL is not enabled with
clk ID 0 index parents.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
clk: mediatek: return XTAL rate directly for gates with XTAL parent
There is currently a massive bug that makes any gate clk that have
CLK_XTAL as parent to return the wrong clock.
Following the code, with CLK_XTAL defined as TOPCKGEN parent, the
topckgen get_rate is called. The clk ID (0) is parsed and only in some
corner case (scenario where fixed clock are not defined) the correct
XTAL rate will be returned as get_factor or get_mux is called (that have
correct handling for CLK_XTAL). With fixed clock defined, the rate that
will be returned will always be the FIRST ELEMENT of the fixed clock
table instead of the hardcoded XTAL rate.
To handle this, add additional logic and if the flag is set to
PARENT_XTAL for the gate, return the XTAL rate directly.
We assume the clk_tree to have xtal_rate defined with clk gates that
have XTAL as parents.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Bevor this commit, only clause 22 access was possible. After this commit,
clause 45 direct access will available as well.
Note that there is a slight change of behavior: Before this commit, the
C45E bit was set to whatever value was left in the register from the
previous access. After this commit, we adopt the common practice of
discerning C45 from C22 using the devad argument.
Signed-off-by: Philip Oberfichtner <pro@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
projects / u-boot.git / log
