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2 years agoarm64: versal: Define zynqmp_mmio_write() for versal
Michal Simek [Thu, 25 Aug 2022 12:59:02 +0000 (06:59 -0600)]
arm64: versal: Define zynqmp_mmio_write() for versal

GQSPI driver is using it but this function is never called for Versal
because it is removed by linker. But function should be declared to avoid
this build warning:
drivers/spi/zynqmp_gqspi.c: In function 'zynqmp_qspi_set_tapdelay':
drivers/spi/zynqmp_gqspi.c:378:3: warning: implicit declaration of function
'zynqmp_mmio_write' [-Wimplicit-function-declaration]
  378 |   zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST,

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220825125906.11581-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agospi: zynqmp_gqspi: Add tap delays for Versal
Ashok Reddy Soma [Thu, 25 Aug 2022 12:59:01 +0000 (06:59 -0600)]
spi: zynqmp_gqspi: Add tap delays for Versal

Add tap delays for Versal platform and re-align the tapdelays code.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220825125906.11581-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agospi: cadence-qspi: Use priv instead of plat across the driver
Ashok Reddy Soma [Wed, 24 Aug 2022 11:38:47 +0000 (05:38 -0600)]
spi: cadence-qspi: Use priv instead of plat across the driver

As per driver model we should enumerate plat structure only in
of_to_plat() and should be used only in probe(). Copy required
plat structure info into priv structure in probe() and use priv
structure across the driver. So replace plat with priv structure across
the driver.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220824113847.7482-4-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agospi: cadence_qspi: Call read_setup for STIG_READ
Ashok Reddy Soma [Wed, 24 Aug 2022 11:38:46 +0000 (05:38 -0600)]
spi: cadence_qspi: Call read_setup for STIG_READ

In cadence_spi_read_id we are using STIG mode to read flash id's.
Call cadence_qspi_apb_command_read_setup() to setup cmd, addr and data
bus width properly before cadence_qspi_apb_command_read().

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220824113847.7482-3-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agospi: cadence-qspi: Correct flash reset function name
Ashok Reddy Soma [Wed, 24 Aug 2022 11:38:45 +0000 (05:38 -0600)]
spi: cadence-qspi: Correct flash reset function name

In cadence_spi_probe, cadence_qspi_versal_flash_reset() is called to reset
the flash device. Looks like there is a mistake in previous series of
patches where it is defined as cadence_spi_versal_flash_reset() but
called as cadence_qspi_versal_flash_reset. Since there is a weak function
defined with the same name this issue was not caught.

Fix the issue by renaming cadence_spi_versal_flash_reset as
cadence_qspi_versal_flash_reset().

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220824113847.7482-2-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agomicroblaze: add arch_print_bdinfo() implementation
Ovidiu Panait [Mon, 29 Aug 2022 17:02:05 +0000 (20:02 +0300)]
microblaze: add arch_print_bdinfo() implementation

Allow bdinfo command to print icache/dcache information:
U-Boot-mONStR> bdinfo
boot_params = 0x00000000
DRAM bank   = 0x00000000
-> start    = 0x04000000
-> size     = 0x04000000
flashstart  = 0x00000000
flashsize   = 0x00000000
flashoffset = 0x00000000
baudrate    = 9600 bps
relocaddr   = 0x07f76000
reloc off   = 0x02f76000
Build       = 32-bit
current eth = unknown
ethaddr     = (not set)
IP addr     = <NULL>
fdt_blob    = 0x07fec7e0
new_fdt     = 0x00000000
fdt_size    = 0x00000000
lmb_dump_all:
 memory.cnt  = 0x1
 memory[0]      [0x4000000-0x7ffffff], 0x04000000 bytes flags: 0
 reserved.cnt  = 0x1
 reserved[0]    [0x7e94b8c-0x7ffffff], 0x0016b474 bytes flags: 0
devicetree  = embed
icache      = 32 KiB
icache line = 4 Bytes
dcache      = 32 KiB
dcache line = 4 Bytes

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220829170205.1274484-4-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agocmd: bdinfo: introduce bdinfo_print_size() helper
Ovidiu Panait [Mon, 29 Aug 2022 17:02:04 +0000 (20:02 +0300)]
cmd: bdinfo: introduce bdinfo_print_size() helper

Add bdinfo_print_size() helper to display size variables (such as cache
sizes) in bdinfo format. The size is printed as "xxx Bytes", "xxx KiB",
"xxx MiB", "xxx GiB", etc as needed;

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Jason Liu <jason.hui.liu@nxp.com>
Link: https://lore.kernel.org/r/20220829170205.1274484-3-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agocpu: microblaze: add error handling in microblaze_cpu_get_desc()
Ovidiu Panait [Mon, 29 Aug 2022 17:02:03 +0000 (20:02 +0300)]
cpu: microblaze: add error handling in microblaze_cpu_get_desc()

Check snprintf() return value for errors.

Make microblaze_cpu_get_desc() directly return snprintf() error code if
ret < 0. Otherwise, if the return value is greater than or equal to size,
the resulting string is truncated, so return -ENOSPC.

Fixes: 816226d27e ("cpu: add CPU driver for microblaze")
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220829170205.1274484-2-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agomicroblaze: drop CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE
Ovidiu Panait [Mon, 29 Aug 2022 17:02:02 +0000 (20:02 +0300)]
microblaze: drop CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE

These macros are not used anymore in microblaze code since commit
f113d7d303467 ("Convert CONFIG_SPL_STACK to Kconfig"), so remove them.

Fixes: f113d7d303467 ("Convert CONFIG_SPL_STACK to Kconfig")
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220829170205.1274484-1-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agonet: gem: Check rate before setting it up
Michal Simek [Fri, 26 Aug 2022 08:30:47 +0000 (10:30 +0200)]
net: gem: Check rate before setting it up

On QEMU setting rate for fixed clock is failing. That's why check a rate
first if the rate is the same there is no need to ask for the change.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/bc465ffd4904bfd65208b782daa06732b915db54.1661502645.git.michal.simek@amd.com
2 years agoxilinx: versal: Disable LMB for mini configurations
Michal Simek [Tue, 6 Sep 2022 10:41:34 +0000 (12:41 +0200)]
xilinx: versal: Disable LMB for mini configurations

There shouldn't be a reason to have LMB on for these configurations.
LMB was already disabled for ZynqMP by commit 0063487a5b60 ("configs:
zynqmp: Disable LMB for mini u-boot").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/17d1e9b50b2fd032352911f94f4f213828e0a3f7.1662460892.git.michal.simek@amd.com
2 years agoarm64: xilinx: Move board_get_usable_ram_top() to common location
Michal Simek [Thu, 25 Aug 2022 12:23:10 +0000 (14:23 +0200)]
arm64: xilinx: Move board_get_usable_ram_top() to common location

The commit ce39ee28ec31 ("zynqmp: Do not place u-boot to reserved memory
location") adds functionality for ZynqMP to read reserved memory node and
do not place U-Boot to reserved location. This functionality is generic
across all Xilinx SOCs that's why move it to common location to be used by
all Xilinx SOCs.

On zynq platform this is also fixing issue where U-Boot was placed to
locating which was reserved already which ends up with error message
"ERROR: reserving fdt memory region failed (addr=30000000 size=10000000
flags=4)" which is shown when bdinfo is called.

Tested on vck190, zcu102, zc706 and kc705 to cover all platforms.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b0817807912f7c7af6a8e1cf9ee04e5ab5de5f6a.1661430188.git.michal.simek@amd.com
2 years agoARM: zynq: Align bss and end of u-boot image to 64bits
Michal Simek [Wed, 31 Aug 2022 09:28:59 +0000 (11:28 +0200)]
ARM: zynq: Align bss and end of u-boot image to 64bits

The main reason is that DT memory reserved code is expecting DT to be 64bit
aligned. For more information take a look at commit 5bd5ee02b23b ("xilinx:
zynqmp: Check that DT is 64bit aligned").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9f3688cda188d8ea0b462df2aa08a10ddcc9c149.1661938136.git.michal.simek@amd.com
2 years agoxilinx: Enable CMD_GREPENV/SETEXPR by default
Michal Simek [Wed, 24 Aug 2022 11:28:35 +0000 (13:28 +0200)]
xilinx: Enable CMD_GREPENV/SETEXPR by default

Enable both of these commands in Xilinx SoCs to be able to use them in boot
scripts.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1a612be7e09e9bc502f30e1f025441ccf8accba5.1661340513.git.michal.simek@amd.com
2 years agoxilinx: Add env redund offset
T Karthik Reddy [Wed, 24 Aug 2022 11:23:26 +0000 (13:23 +0200)]
xilinx: Add env redund offset

ENV_OFFSET_REDUND config is by default set to 0 for flashes. Saving the env
variables is overwriting data at 0 offset, which is wrong. So add default
redund env offset for Zynq, ZynqMP, Versal and microblaze platforms.
Configured ENV_OFFSET_REDUND offsets by ENV_OFFSET + (2 * ENV_SIZE).

In case of versal, we configured ENV_OFFSET_REDUND at 0x7F00000 instead
of 0x7F80000. As BOOT_SCRIPT_OFFSET is already configured at 0x7F80000.

Added ENV_OFFSET_REDUND in Kconfig for microblaze due to dependency of
ENV_IS_IN_SPI_FLASH config.

Below table specifies platform specific env and env redund offsets.

PLAT ENV_OFFSET ENV_OFFSET_REDUND
---- ---------- -----------------
ZYNQ 0xE0000 0xE40000
ZYNQMP 0x1E00000 0x1E80000
VERSAL 0x7F40000 0x7F00000
MICROBLAZE 0x1080000 0x10C0000

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/92656dc08f0f5a749d62b71ca6e77fe1be72e9e0.1661340204.git.michal.simek@amd.com
2 years agoarm64: zynqmp: add ref_clk property for REFCLKPER calculation
Piyush Mehta [Tue, 23 Aug 2022 13:03:31 +0000 (15:03 +0200)]
arm64: zynqmp: add ref_clk property for REFCLKPER calculation

Added ref_clk 'ref' property for GUCTL_REFCLKPER and GFLADJ_REFCLK_FLADJ
calculation. This property configure correct value for SOF/ITP counter
and period of ref_clk.
This patch adds 'ref' property for both dwc3_0 and dwc3_1 cores.

Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/417545b948ea12a9301a5e80851f98523be2b443.1661259809.git.michal.simek@amd.com
2 years agoarm64: zynqmp: Add missing tca6416 to zynqmp SC
Michal Simek [Tue, 23 Aug 2022 13:00:25 +0000 (15:00 +0200)]
arm64: zynqmp: Add missing tca6416 to zynqmp SC

Add missing tca6416 i2c gpio controller to SC dts file.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a19c191d0dffb213d9dc8809d22728d79cf73a22.1661259623.git.michal.simek@amd.com
2 years agoarm: dts: Add xlnx prefix to GEM compatible string
Harini Katakam [Tue, 23 Aug 2022 12:59:20 +0000 (14:59 +0200)]
arm: dts: Add xlnx prefix to GEM compatible string

cdns,zynq/zynqmp were recentle deprecated in Linux in favour of xlnx
prefix. Add this new compatible string and retain the existing string for
compatibility with uboot drivers.

Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a38b1b55132fc026cc09224dba61e42fd03b1a36.1661259558.git.michal.simek@amd.com
2 years agoarm64: zynqmp: Add mtd partition for secure OS storage area
Amit Kumar Mahapatra [Tue, 23 Aug 2022 08:18:03 +0000 (10:18 +0200)]
arm64: zynqmp: Add mtd partition for secure OS storage area

Update MTD partitions of Kria device trees to allocate 128KB of QSPI
memory for secure OS. Increased "SHA256" partition size & changed
starting address of "User" partition to accommodate the new partition
"Secure OS Storage"

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9cc64b8c731d11439de73d0af54c65080068f00b.1661242681.git.michal.simek@amd.com
2 years agoxilinx: Define only mmc devnum not partition
Michal Simek [Tue, 9 Aug 2022 14:32:54 +0000 (16:32 +0200)]
xilinx: Define only mmc devnum not partition

The commit 53b406369e9d ("DFU: Check the number of arguments and argument
string strictly") added strict control over string that 0:1 partition
definition is not valid anymore that's why use only device number without
partition ID. Device is specified by 2nd parameter and partition by 3rd.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/840eca944f4f2abeeb63b5d724f9ba5fe9a9213b.1660055571.git.michal.simek@amd.com
2 years agoxilinx: zynq: Use CONFIG_SPL_FS_LOAD_PAYLOAD_NAME for dfu_alt_info
Michal Simek [Tue, 9 Aug 2022 14:32:53 +0000 (16:32 +0200)]
xilinx: zynq: Use CONFIG_SPL_FS_LOAD_PAYLOAD_NAME for dfu_alt_info

CONFIG_SPL_FS_LOAD_PAYLOAD_NAME stores the name of firmware file to be
loaded by SPL. Name can be selected via Kconfig that's why use the macro.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/601fbc2dfd16b4708fc6b5f86954e10add43334e.1660055571.git.michal.simek@amd.com
2 years agoxilinx: Fix logic when dfu_alt_info is generated
Michal Simek [Tue, 9 Aug 2022 14:32:52 +0000 (16:32 +0200)]
xilinx: Fix logic when dfu_alt_info is generated

Generate dfu_alt_info only when it is not defined.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/464e4b325c644e52a660df9cf44eeb4d80427f6a.1660055571.git.michal.simek@amd.com
2 years agoxilinx: zynq: Enable mkeficapsule tools compilation
Michal Simek [Tue, 9 Aug 2022 14:32:51 +0000 (16:32 +0200)]
xilinx: zynq: Enable mkeficapsule tools compilation

Zynq can use efi capsule infrastructure that's why enable it by default.
For capsule generation for zynq you can use:

pushd spl
../tools/mkeficapsule -g "1ba29a15-9969-40aa-b424-e86121618664" boot.bin \
--index 1 ../capsule1.bin
popd
./tools/mkeficapsule -g "1a5178f0-87d3-4f36-ac63-3b31a23be305" u-boot.img \
--index 2 capsule2.bin

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a8194ecfa7932f2d8ada5ee508b2a026c782f15e.1660055571.git.michal.simek@amd.com
2 years agoxilinx: versal: Define CONFIG_CQSPI_REF_CLK
Ashok Reddy Soma [Fri, 5 Aug 2022 09:19:58 +0000 (11:19 +0200)]
xilinx: versal: Define CONFIG_CQSPI_REF_CLK

With commit 55b3ba4c2ba4 ("spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK
to Kconfig") CONFIG_CQSPI_REF_CLK is moved to Kconfig.

The static value via Kconfig is a fallback option in case of clock
framework is not enabled or fails for some reason.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fe7c38a19e878c307d5b75311bbfd8cf6c1f601e.1659691195.git.michal.simek@amd.com
2 years agoxilinx: versal: Enable power domain driver
Ashok Reddy Soma [Fri, 5 Aug 2022 09:19:57 +0000 (11:19 +0200)]
xilinx: versal: Enable power domain driver

Enable power domain driver to request node for all the IP's that are
enabled in DT.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/dbed54df622d647b8d520d8ce5289cd69ba66e0b.1659691195.git.michal.simek@amd.com
2 years agofirmware: zynqmp: Skip loading config object for Versal
Ashok Reddy Soma [Fri, 5 Aug 2022 09:19:56 +0000 (11:19 +0200)]
firmware: zynqmp: Skip loading config object for Versal

SET_CONFIGURATION is not yet implemented for Versal platforms. Skip
loading config object for Versal until support is added.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/eb7ef6c6de36a1f7d056de43042f96fe3639f18e.1659691195.git.michal.simek@amd.com
2 years agoxilinx: zynq: Disable LMB for mini configurations
Michal Simek [Tue, 6 Sep 2022 10:41:10 +0000 (12:41 +0200)]
xilinx: zynq: Disable LMB for mini configurations

There shouldn't be a reason to have LMB on for these configurations.
LMB was already disabled for ZynqMP by commit 0063487a5b60 ("configs:
zynqmp: Disable LMB for mini u-boot").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/07d95f619a15672d1a234eddcfbb54c0ab382eaa.1662460867.git.michal.simek@amd.com
2 years agoxilinx: zynqmp: Disable LMB for mini u-boot
Ashok Reddy Soma [Fri, 5 Aug 2022 09:19:55 +0000 (11:19 +0200)]
xilinx: zynqmp: Disable LMB for mini u-boot

LMB is not required for mini u-boot which runs out of on chip memory.
Disable CONFIG_LMB from mini u-boot defconfig's.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/45fad28825f0f236ad45e700aca1f39afbb22236.1659691195.git.michal.simek@amd.com
2 years agocmd: bdinfo: Enable dumping lmb data when LMB is enabled
Michal Simek [Wed, 7 Sep 2022 07:52:09 +0000 (09:52 +0200)]
cmd: bdinfo: Enable dumping lmb data when LMB is enabled

The commit 9996cea75f5a ("lmb/bdinfo: dump lmb info via bdinfo") added
support for dumping LMB information as the part of bdinfo. But code itself
should be called only when LMB is enabled.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/3e40c8bb77550dfca9f7eb48fe644a018d971411.1662537127.git.michal.simek@amd.com
2 years agoxilinx: zynqmp: Disable various configs for mini U-Boot
Ashok Reddy Soma [Fri, 5 Aug 2022 09:19:54 +0000 (11:19 +0200)]
xilinx: zynqmp: Disable various configs for mini U-Boot

With 2022.01-rc3 upgrade, the size of the mini U-Boot increased and is
not able to fit in OCM. Hence disable unnecessary configs and make room.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/306b57818601fa3571bc75c4182f25aaa3f2a793.1659691195.git.michal.simek@amd.com
2 years agoxilinx: versal: Enable i2c mux uclass with pca954x driver
Michal Simek [Fri, 5 Aug 2022 09:19:53 +0000 (11:19 +0200)]
xilinx: versal: Enable i2c mux uclass with pca954x driver

Xilinx is using pca954x i2c muxes on a lot of boards that's why enable this
driver by default.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c090aea3436c7a4ebe698da6cbc70e70a14baae3.1659691195.git.michal.simek@amd.com
2 years agoxilinx: zynqmp: Fix AES with a user provided key
Janne Ylalehto [Tue, 16 Aug 2022 12:45:25 +0000 (15:45 +0300)]
xilinx: zynqmp: Fix AES with a user provided key

The user provided key address was not flushed in struct aes because of
the flushing location in the function.

Signed-off-by: Janne Ylalehto <ylalehto@gmail.com>
Link: https://lore.kernel.org/r/20220816124525.19671-1-ylalehto@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agofpga: zynq: Remove post config info message for SPL
Stefan Herbrechtsmeier [Mon, 8 Aug 2022 14:53:31 +0000 (16:53 +0200)]
fpga: zynq: Remove post config info message for SPL

The drivers informs the user that a post config was not run after FPGA
configuration. This message is unnecessary in SPL because the
ps7_post_config function is called via spl_board_prepare_for_boot
function before jump_to_image_no_args function from board_init_r
function.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220808145331.24723-1-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agozynq: Convert arm twd timer to DM driver
Stefan Herbrechtsmeier [Fri, 5 Aug 2022 06:16:28 +0000 (08:16 +0200)]
zynq: Convert arm twd timer to DM driver

Move arm twd timer driver from zynq to generic location.

DM timer drivers are designed differently to original driver. Timer is
counting up and not down.
Information about clock rates are find out in timer_pre_probe() that's
why there is no need to get any additional information from DT in the
driver itself (only register offset).

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220805061629.1207-1-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agoMerge branch '2022-09-02-assorted-improvements' into next
Tom Rini [Sat, 3 Sep 2022 01:51:21 +0000 (21:51 -0400)]
Merge branch '2022-09-02-assorted-improvements' into next

- DM RTC improvements that should help in CI, allow disabling LTO from
  the make line, add extension (cape, etc) support to distro bootcmd,
  add a pause command and re-enable ARM v4T support.

2 years agodm: rtc: Try to handle the localtime() race
Simon Glass [Mon, 1 Aug 2022 13:58:48 +0000 (07:58 -0600)]
dm: rtc: Try to handle the localtime() race

At present the sandbox timer uses localtime() which can jump around twice
a year when daylight-saving time changes.

It would be tricky to make use of gmtime() since we still need to present
the time in local time, as seems to be required by U-Boot's RTC interface.

The problem can only happen once, so use a loop to detect it and try
again. This should be sufficient to detect either a change in the 'second'
value, or a daylight-saving change. We can assume that the latter also
incorporates a 'second' change, so there is no need to loop more than
twice.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 years agodm: rtc: Try to avoid a race in rtc_set_get test
Simon Glass [Mon, 1 Aug 2022 13:58:47 +0000 (07:58 -0600)]
dm: rtc: Try to avoid a race in rtc_set_get test

It seems that the time can change in between getting it and reading the
offset. Check for this and try again if this happens.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 years agodm: rtc: Avoid a race in the rtc_reset test
Simon Glass [Mon, 1 Aug 2022 13:58:46 +0000 (07:58 -0600)]
dm: rtc: Avoid a race in the rtc_reset test

Since resetting the RTC on sandbox causes it to read the base time from
the system, we cannot rely on this being unchanged since it was last read.
Allow for a one-second delay.

Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Fixes: https://source.denx.de/u-boot/u-boot/-/issues/4
Reported-by: Bin Meng <bmeng.cn@gmail.com>
Reported-by: Tom Rini <trini@konsulko.com>
Suggested-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Simon Glass <sjg@chromium.org>
2 years agotest: Allow running tests multiple times
Simon Glass [Mon, 1 Aug 2022 13:58:45 +0000 (07:58 -0600)]
test: Allow running tests multiple times

Some tests can have race conditions which are hard to detect on a single
one. Add a way to run tests more than once, to help with this.

Each individual test is run the requested number of times before moving
to the next test. If any runs failed, a message is shown.

This is most useful when running a single test, since running all tests
multiple times can take a while.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 years agodm: rtc: Make use of ut_assertnonnull()
Simon Glass [Mon, 1 Aug 2022 13:58:44 +0000 (07:58 -0600)]
dm: rtc: Make use of ut_assertnonnull()

Use this (newish) macro since it is designed for the purpose of making
sure things are non-NULL.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 years agoci: Add a test for a non-LTO build
Simon Glass [Wed, 3 Aug 2022 18:13:09 +0000 (12:13 -0600)]
ci: Add a test for a non-LTO build

Check that sandbox builds and runs tests OK with LTO disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 years agoMakefile: Allow LTO to be disabled for a build
Simon Glass [Wed, 3 Aug 2022 18:13:08 +0000 (12:13 -0600)]
Makefile: Allow LTO to be disabled for a build

LTO (Link-Time Optimisation) is an very useful feature which can
significantly reduce the size of U-Boot binaries. So far it has been
made available for selected ARM boards and sandbox.

However, incremental builds are much slower when LTO is used. For example,
an incremental build of sandbox takes 2.1 seconds on my machine, but 6.7
seconds with LTO enabled.

Add a NO_LTO parameter to the build, similar to NO_SDL, so it can be
disabled during development if needed, for faster builds.

Add some documentation about LTO while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2 years agoarm: ARMv4 assembly compatibility
Sergei Antonov [Sun, 21 Aug 2022 13:34:20 +0000 (16:34 +0300)]
arm: ARMv4 assembly compatibility

There is currently a problem that U-Boot can not work on ARMv4
because assembly imlementations of memcpy() and some other functions
use "bx lr" instruction that is not available on ARMv4 ("mov pc, lr"
should be used instead).

A working preprocessor-based solution to this problem is found in
arch/arm/lib/relocate.S. Move it to the "ret" macro in
arch/arm/include/asm/assembler.h and change all "bx lr" code
to "ret lr" in functions that may run on ARMv4. Linux source code
deals with this problem in the same manner.

v1 -> v2:
Comment update. Pointed out by Andre Przywara.

Signed-off-by: Sergei Antonov <saproj@gmail.com>
CC: Samuel Holland <samuel@sholland.org>
CC: Ye Li <ye.li@nxp.com>
CC: Simon Glass <sjg@chromium.org>
CC: Andre Przywara <andre.przywara@arm.com>
CC: Marek Vasut <marex@denx.de>
CC: Sean Anderson <sean.anderson@seco.com>
CC: Tom Rini <trini@konsulko.com>
2 years agocmd: Add pause command
Samuel Dionne-Riel [Thu, 18 Aug 2022 19:44:04 +0000 (15:44 -0400)]
cmd: Add pause command

This command is being introduced with the goal of allowing user-friendly
"generic use case" U-Boot builds to pause until user input under some
situations.

The main use case would be when a boot failure happens, to pause until
the user has had time to acknowledge the current state.

Tested using:

    make && ./u-boot -v -T -c 'ut lib lib_test_hush_pause'

Signed-off-by: Samuel Dionne-Riel <samuel@dionne-riel.com>
Cc: Simon Glass <sjg@chromium.org>
2 years agodistro_bootcmd: Introduce support for extension command
Matwey V. Kornilov [Tue, 9 Aug 2022 15:54:07 +0000 (18:54 +0300)]
distro_bootcmd: Introduce support for extension command

Try to load required DTB overlays if the board supports extensions and
CONFIG_CMD_EXTENSION is enabled.

Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
2 years agoMerge branch '2022-09-01-assorted-Kconfig-migrations' into next
Tom Rini [Fri, 2 Sep 2022 12:59:15 +0000 (08:59 -0400)]
Merge branch '2022-09-01-assorted-Kconfig-migrations' into next

- Assorted Kconfig migrations

2 years agoARM: imx6: dh-imx6: Enable d-cache early in SPL
Marek Vasut [Wed, 17 Aug 2022 13:07:14 +0000 (15:07 +0200)]
ARM: imx6: dh-imx6: Enable d-cache early in SPL

Enable d-cache early in SPL right after DRAM is started up.
This reduces U-Boot proper load time by 650ms when loaded
from SPI NOR.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Philip Oberfichtner <pro@denx.de>
2 years agoARM: cache: Allow SPL to build cache-pl310.c
Philip Oberfichtner [Wed, 17 Aug 2022 13:07:13 +0000 (15:07 +0200)]
ARM: cache: Allow SPL to build cache-pl310.c

Introduce the new Kconfig symbol CONFIG_SPL_SYS_L2_PL310 to allow the
SPL to build cache-pl310.c.

Before this commit, the SPL could enable the PL310 L2 cache [1], but the
cache maintenance functions from cache-pl310.c were only useable for
non-SPL builds.

After enabling the cache one must be able to flush it, too. Thus this
commit allows cache-pl310.c to be included in the SPL build.

[1] See for example arch/arm/mach-imx/cache.c: v7_outer_cache_enable()

Signed-off-by: Philip Oberfichtner <pro@denx.de>
2 years agoConvert CONFIG_SYS_L2_PL310 to Kconfig
Philip Oberfichtner [Wed, 17 Aug 2022 13:07:12 +0000 (15:07 +0200)]
Convert CONFIG_SYS_L2_PL310 to Kconfig

This converts CONFIG_SYS_L2_PL310 to Kconfig.

For omap2 and mvebu the 'select SYS_L2_PL310' locations were
determined using ./tools/moveconfig -i CONFIG_SYS_L2_PL310.

For mx6 I manually chose ARCH_MX6 as 'select' location. The
correctness has been verified using

$ ./tools/moveconfig.py -f ARCH_MX6 ~SYS_L2_PL310 ~SYS_L2CACHE_OFF
0 matches

That means whenever an ARCH_MX6 board had SYS_L2_PL310 disabled, this
was correctly reflected in SYS_L2CACHE_OFF. Thus it's safe to insert
the 'select' statement under ARCH_MX6.

Signed-off-by: Philip Oberfichtner <pro@denx.de>
2 years agoRemove CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS et al
Tom Rini [Wed, 10 Aug 2022 14:29:28 +0000 (10:29 -0400)]
Remove CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS et al

This removes the following symbols:
   CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS
   CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS
   CONFIG_SYS_I2C_LDI_ADDR
   CONFIG_SYS_I2C_DVI_ADDR
   CONFIG_SYS_I2C_DVI_BUS_NUM

They are unused by any code in tree at this time.

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoConvert CONFIG_SYS_I2C_EEPROM_CCID et al to Kconfig
Tom Rini [Wed, 10 Aug 2022 14:29:27 +0000 (10:29 -0400)]
Convert CONFIG_SYS_I2C_EEPROM_CCID et al to Kconfig

This converts the following to Kconfig:
   CONFIG_SYS_I2C_EEPROM_CCID
   CONFIG_SYS_I2C_EEPROM_NXID
   CONFIG_SYS_EEPROM_BUS_NUM

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoMerge branch '2022-08-26-assorted-platform-updates' into next
Tom Rini [Fri, 26 Aug 2022 18:47:48 +0000 (14:47 -0400)]
Merge branch '2022-08-26-assorted-platform-updates' into next

- Assorted Arm, TI and Qualcomm platform updates

2 years agofirmware: ti_sci: Move ACK checking to ti_sci_do_xfer() function
Andrew Davis [Tue, 26 Jul 2022 01:25:06 +0000 (20:25 -0500)]
firmware: ti_sci: Move ACK checking to ti_sci_do_xfer() function

We can check if the message was acknowledged in the common
ti_sci_do_xfer() which lets us remove it from after each call to this
function. This simplifies the code and reduces binary size.

Signed-off-by: Andrew Davis <afd@ti.com>
2 years agofirmware: ti_sci: Remove inline keyword from functions
Andrew Davis [Tue, 26 Jul 2022 01:25:05 +0000 (20:25 -0500)]
firmware: ti_sci: Remove inline keyword from functions

The inline hint is not needed here, the compiler will do the right thing
based on if we are compiling for speed or for code size. In this case the
inline causes this function to be placed inside each callsite which is
not the right thing to do for either speed nor size. There is no
performance benefit to this due to the larger function size reducing
cache locality, but there is a huge size penalty. Remove inline keyword.

Signed-off-by: Andrew Davis <afd@ti.com>
2 years agofirmware: ti_sci: Factor out message alloc failed message
Andrew Davis [Tue, 26 Jul 2022 01:25:04 +0000 (20:25 -0500)]
firmware: ti_sci: Factor out message alloc failed message

We don't need to print the same message in every location, just
print it in the function that fails and remove all the extra
message printouts.

Signed-off-by: Andrew Davis <afd@ti.com>
2 years agofirmware: ti_sci: Reduce output on ti_sci_do_xfer error
Andrew Davis [Tue, 26 Jul 2022 01:25:03 +0000 (20:25 -0500)]
firmware: ti_sci: Reduce output on ti_sci_do_xfer error

This ti_sci_do_xfer() function already prints out the reason for the
failure, and the caller of each of these functions should also notify
the user of the failed task. Remove this extra level of error message.

Signed-off-by: Andrew Davis <afd@ti.com>
2 years agoarm: dts: qcom: Sync pinctrl DT nodes with Linux bindings
Sumit Garg [Wed, 27 Jul 2022 08:22:04 +0000 (13:52 +0530)]
arm: dts: qcom: Sync pinctrl DT nodes with Linux bindings

Currently for all Qcom SoCs/boards there are separate compatibles for
GPIO and pinctrl. But this is inconsistent with official (upstream) Linux
bindings which requires only a single compatible "qcom,<SoC name>-pinctrl"
and there is no such compatible property as "qcom,tlmm-<SoC name>".

So fix this inconsistency for Qcom SoCs in order to comply with upstream
DT bindings. This is done via removing compatibles from "msm_gpio" driver
and via binding to "msm_gpio" driver from pinctrl driver in case
"gpio-controller" property is specified for pinctrl node.

Suggested-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2 years agopinctrl: sdm845: Remove redundant CONFIG_SDM845 check
Sumit Garg [Wed, 27 Jul 2022 08:22:03 +0000 (13:52 +0530)]
pinctrl: sdm845: Remove redundant CONFIG_SDM845 check

DT compatible is sufficient to make platform specific differentiation,
so remove redundant CONFIG_SDM845 check.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2 years agoqcs404evb_defconfig: Enable USB configs
Sumit Garg [Thu, 4 Aug 2022 14:27:21 +0000 (19:57 +0530)]
qcs404evb_defconfig: Enable USB configs

Enable USB config options along with its dependencies like PHY, RESET,
PMIC GPIO etc. config options.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2 years agoboard: qcs404-evb: Enable USB3 specific PMIC GPIO
Sumit Garg [Thu, 4 Aug 2022 14:27:20 +0000 (19:57 +0530)]
board: qcs404-evb: Enable USB3 specific PMIC GPIO

For USB3 host controller to detect devices on the bus it is required to
enable a PMIC GPIO: usb_vbus_boost_pin. So enable that during board
specific initialization.

And since this PMIC GPIO parsing is quite u-boot specific, so add a
DT override to qcs404-evb-uboot.dtsi to represent usb_vbus_boost_pin.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2 years agodts: qcs404-evb: Add PMIC GPIO controller node
Sumit Garg [Thu, 4 Aug 2022 14:27:19 +0000 (19:57 +0530)]
dts: qcs404-evb: Add PMIC GPIO controller node

PMIC GPIOs are special GPIOs which are accessible through SPMI bus. So
add corresponding DT nodes.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2 years agogpio: qcom_pmic: Add support for GPIO LV/MV subtype
Sumit Garg [Thu, 4 Aug 2022 14:27:18 +0000 (19:57 +0530)]
gpio: qcom_pmic: Add support for GPIO LV/MV subtype

GPIO LV (low voltage)/MV (medium voltage) subtypes have different
features and register mappings than 4CH/8CH subtypes. Add support
for LV and MV subtypes.

With GPIO LV/MV subtype available, add "qcom,pms405-gpio" compatible
which requires support for GPIO MV subtype.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2 years agopmic: Convert pm8916 driver to a generic Qcom PMIC driver
Sumit Garg [Thu, 4 Aug 2022 14:27:17 +0000 (19:57 +0530)]
pmic: Convert pm8916 driver to a generic Qcom PMIC driver

Since both pm8916.c and pm8916_gpio.c are already supporting multiple
Qcom SoCs, it makes sense to rename these drivers to pmic_qcom.c and
qcom_pmic_gpio.c respectively. Also, these driver can be extended to
support additional functionality if required for other Qcom SoCs.

Along with this import latest DT binding: qcom,spmi-pmic.txt from Linux
kernel and thereby remove pm8916.txt.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2 years agodts: qcs404-evb: Add USB controller and PHY nodes
Sumit Garg [Thu, 4 Aug 2022 14:27:16 +0000 (19:57 +0530)]
dts: qcs404-evb: Add USB controller and PHY nodes

QCS404 SoC provides support for two USB controllers: one USB3 and the
other one being USB2. The USB3 controller supports further 2 PHY: one high
speed PHY and the other super speed PHY. The USB2 controller supports a
single high speed PHY. So add corresponding DT nodes.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2 years agoclocks: qcs404: Add support for USB clocks
Sumit Garg [Thu, 4 Aug 2022 14:27:15 +0000 (19:57 +0530)]
clocks: qcs404: Add support for USB clocks

Add support for USB controller and PHY clocks for QCS404 SoC.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2 years agoclocks: qcom: Add clock enable callback support
Sumit Garg [Thu, 4 Aug 2022 14:27:14 +0000 (19:57 +0530)]
clocks: qcom: Add clock enable callback support

Drivers like USB, ethernet etc. uses ".enable" hook to enable clocks.
So add corresponding support for Qcom clock drivers.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2 years agodts: qcs404-evb: Add reset controller node
Sumit Garg [Thu, 4 Aug 2022 14:27:13 +0000 (19:57 +0530)]
dts: qcs404-evb: Add reset controller node

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2 years agoreset: qcom: Add support for QCS404 SoC reset table
Sumit Garg [Thu, 4 Aug 2022 14:27:12 +0000 (19:57 +0530)]
reset: qcom: Add support for QCS404 SoC reset table

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2 years agoreset: Convert ipq4019 driver to a generic Qcom driver
Sumit Garg [Thu, 4 Aug 2022 14:27:11 +0000 (19:57 +0530)]
reset: Convert ipq4019 driver to a generic Qcom driver

Since the base functionality remains the same for a reset driver on Qcom
SoCs, so leverage that to convert ipq4019 specific reset driver to a
generic Qcom reset driver. With that one just need to provide SoC specific
reset table.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2 years agophy: Add support for drivers to enable USB on QCS404 SoC
Sumit Garg [Thu, 4 Aug 2022 14:27:10 +0000 (19:57 +0530)]
phy: Add support for drivers to enable USB on QCS404 SoC

QCS404 SoC supports two types of PHY, one supports high speed mode or
USB2 PHY and the other supports super speed mode or USB3 PHY. So add
corresponding PHY drivers.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2 years agophy: Move qcom SoCs specific phy drivers to qcom folder
Sumit Garg [Thu, 4 Aug 2022 14:27:09 +0000 (19:57 +0530)]
phy: Move qcom SoCs specific phy drivers to qcom folder

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2 years agoarm: total_compute: enable psci
Davidson K [Tue, 9 Aug 2022 10:26:52 +0000 (15:56 +0530)]
arm: total_compute: enable psci

psci is used for system reset

Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
2 years agoconfigs: j721s2_evm_a72_defconfig: fix the bootcmd
Jayesh Choudhary [Tue, 2 Aug 2022 13:08:14 +0000 (18:38 +0530)]
configs: j721s2_evm_a72_defconfig: fix the bootcmd

Remove the main_cpsw0_qsgmii_phyinit variable from the boot
command as there is no ethernet firmware in j721s2.

Fixes: 8886341aa670 ('configs: j721s2_evm_a72_defconfig: Add A72 specific defconfig')
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
2 years agoMerge commit 'ac30d240dbb520d0980f0687630feb702a14f51a' of https://source.denx.de...
Tom Rini [Wed, 24 Aug 2022 21:30:29 +0000 (17:30 -0400)]
Merge commit 'ac30d240dbb520d0980f0687630feb702a14f51a' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash into next

Re-sync again on some linux part, add some fixes for fsl_elbc from
Pali and switch
imx8mn bsh to use nand base ident

For nand subsystem tested on:
 - imx8mn  Macronix MX30LF4G18AC
 - P2020 based board Turris 1.1 for fsl_elbc

2 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-marvell
Tom Rini [Tue, 23 Aug 2022 19:44:54 +0000 (15:44 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell

- kirkwood: pogo_v4 & nsa310s: Add distro boot (Tony)
- kirkwood: add DM timer support and use it on lsxl boards (Michael)
- kirkwood: convert the Buffalo Linkstation LS-CHLv2 and XHL boards
  to DM (Michael)
- mvebu: turris_mox/omnia: misc improments (Pali)
- mvebu: mbus: Fix mbus driver to work also after U-Boot relocation (Pali)

2 years agoconfigs: Resync with savedefconfig
Tom Rini [Tue, 23 Aug 2022 19:24:14 +0000 (15:24 -0400)]
configs: Resync with savedefconfig

Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoboard: lsxl: update the README
Michael Walle [Wed, 17 Aug 2022 19:38:09 +0000 (21:38 +0200)]
board: lsxl: update the README

Update the board's README to reflect all the recent changes.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoboard: lsxl: disable eth0
Michael Walle [Wed, 17 Aug 2022 19:38:08 +0000 (21:38 +0200)]
board: lsxl: disable eth0

The board has only one network interface. The linux kernel will
gracefully skip a the ethernet interface if no connected PHY could be
probed. u-boot on the other hand will throw an error message. The kernel
device tree is about to be fixed. For now, just disable the ethernet
interface in our -u-boot.dtsi.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoboard: lsxl: convert to CONFIG_TIMER
Michael Walle [Wed, 17 Aug 2022 19:38:07 +0000 (21:38 +0200)]
board: lsxl: convert to CONFIG_TIMER

Enable the orion timer driver and we are good.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoboard: lsxl: convert to DM_SERIAL
Michael Walle [Wed, 17 Aug 2022 19:38:06 +0000 (21:38 +0200)]
board: lsxl: convert to DM_SERIAL

DM_SERIAL needs early malloc. The on-chip RAM is pretty tight, it's only
2kiB, with DM_SERIAL enabled, this doesn't work anymore. Fortunately for
us, we don't need the on-chip RAM because the DRAM is already
initialized before u-boot starts. Just put the early malloc area there
and use the default early malloc size.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoboard: lsxl: convert to DM_ETH
Michael Walle [Wed, 17 Aug 2022 19:38:05 +0000 (21:38 +0200)]
board: lsxl: convert to DM_ETH

Just enabling the Kconfig option for DM_ETH and DM_MDIO is enough.
Additionally, we can remove the old hardcoded config.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoboard: lsxl: convert to DM_GPIO
Michael Walle [Wed, 17 Aug 2022 19:38:04 +0000 (21:38 +0200)]
board: lsxl: convert to DM_GPIO

Use the new mvebu GPIO driver and convert all the function calls to the
former kirkwood GPIO driver. This means that we are now using the LED
uclass and the regulator uclass. Unfortunately, the GPIO LED doesn't
offer a blinking method. Thus we are now stuck with solid on and off
states, which makes debugging a bit harder. Also, there is no GPIO fan
driver for now.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoboard: lsxl: make last resort recovery more reliable
Michael Walle [Wed, 17 Aug 2022 19:38:03 +0000 (21:38 +0200)]
board: lsxl: make last resort recovery more reliable

If something is wrong with the environment, we cannot rely on a proper
u-boot operation anymore. In fact, it is possible, that we never reach
misc_init_r() with a broken environment.

Also don't enable the netconsole by environment settings. This way the
user don't have to reconfigure the environment. Instead the network
console is only enabled when the push button is pressed during boot.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoboard: lsxl: enable ATAGS support
Michael Walle [Wed, 17 Aug 2022 19:38:02 +0000 (21:38 +0200)]
board: lsxl: enable ATAGS support

We still need to be able to boot legacy images. Esp. the debian
installer will have a kernel with an appended DTB.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoboard: lsxl: use proper *_r variables
Michael Walle [Wed, 17 Aug 2022 19:38:01 +0000 (21:38 +0200)]
board: lsxl: use proper *_r variables

Use the common kernel_addr_r, ramdisk_addr_r and fdt_addr_r variable
names.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoboard: lsxl: reorder image loading and remove ramdisk_len
Michael Walle [Wed, 17 Aug 2022 19:38:00 +0000 (21:38 +0200)]
board: lsxl: reorder image loading and remove ramdisk_len

We can load the ramdisk as the last step. This way we don't have to set
the intermediate variable 'ramdisk_len' and can remove it.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoboard: lsxl: use CONFIG_DEFAULT_FDT_FILE
Michael Walle [Wed, 17 Aug 2022 19:37:59 +0000 (21:37 +0200)]
board: lsxl: use CONFIG_DEFAULT_FDT_FILE

Drop our own CONFIG_FDTFILE handling in favor of the generic
CONFIG_DEFAULT_FDT_FILE one.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoboard: lsxl: automatically select CONFIG_MISC_INIT_R
Michael Walle [Wed, 17 Aug 2022 19:37:58 +0000 (21:37 +0200)]
board: lsxl: automatically select CONFIG_MISC_INIT_R

The board code needs this to be set. Otherwise, the recovery mechanism
doesn't work. Therefore, select this option automatically with the
board.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoboard: lsxl: remove unused header files
Michael Walle [Wed, 17 Aug 2022 19:37:57 +0000 (21:37 +0200)]
board: lsxl: remove unused header files

Cleanup the included header files in the board code. These are all
leftovers from earlier days.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoboard: lsxl: remove CONFIG_ENV_OVERWRITE
Michael Walle [Wed, 17 Aug 2022 19:37:56 +0000 (21:37 +0200)]
board: lsxl: remove CONFIG_ENV_OVERWRITE

This is not needed. The user can force setting the variables with
"setenv -f".

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoboard: lsxl: remove eraseenv script
Michael Walle [Wed, 17 Aug 2022 19:37:55 +0000 (21:37 +0200)]
board: lsxl: remove eraseenv script

This is not needed. The user can do a "env default -f -a".

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoboard: lsxl: remove unused features
Michael Walle [Wed, 17 Aug 2022 19:37:54 +0000 (21:37 +0200)]
board: lsxl: remove unused features

Make the binary smaller by removing unused features.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoboard: lsxl: limit size to 384kiB
Michael Walle [Wed, 17 Aug 2022 19:37:53 +0000 (21:37 +0200)]
board: lsxl: limit size to 384kiB

The board only has a 4Mbit flash and two sectors are reserved for the
u-boot environment and the device tree.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agobutton: gpio: add DM_GPIO dependency
Michael Walle [Wed, 17 Aug 2022 19:37:52 +0000 (21:37 +0200)]
button: gpio: add DM_GPIO dependency

The gpio-button driver depends on DM_GPIO, add it to Kconfig to avoid
build errors.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agotimer: add orion-timer support
Michael Walle [Wed, 17 Aug 2022 19:37:51 +0000 (21:37 +0200)]
timer: add orion-timer support

Add timer support for Kirkwood and MVEBU devices.

Cc: Pali Rohár <pali@kernel.org>
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoarm: kirkwood: make it CONFIG_TIMER aware
Michael Walle [Wed, 17 Aug 2022 19:37:50 +0000 (21:37 +0200)]
arm: kirkwood: make it CONFIG_TIMER aware

If we switch to CONFIG_TIMER, we don't need the legacy timer macros and
functions anymore. Add the proper guards to exclude them from compiling.

Cc: Pali Rohár <pali@kernel.org>
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoarm: kirkwood: 88f6281: Detect CONFIG_SYS_TCLK from SAR register
Pali Rohár [Wed, 17 Aug 2022 19:37:49 +0000 (21:37 +0200)]
arm: kirkwood: 88f6281: Detect CONFIG_SYS_TCLK from SAR register

Bit 21 in SAR register specifies if TCLK is running at 166 MHz or 200 MHz.
This information is undocumented in public Marvell Kirkwood Functional
Specifications [2], but is available in Linux v3.15 kirkwood code [1].

Commit 8ac303d49f89 ("arm: kirkwood: Do not overwrite CONFIG_SYS_TCLK")
broke support for Marvell 88F6281 SoCs because it was expected that all
those SoCs have TCLK running at 200 MHz as specified in Marvell 88F6281
Hardware Specifications [3].

Fix broken support for 88F6281 by detecting CONFIG_SYS_TCLK from SAR
register, like it was doing Linux v3.15.

[1] - https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/arch/arm/mach-kirkwood/common.c?h=v3.15#n542
[2] - https://web.archive.org/web/20130730091033/http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
[3] - https://web.archive.org/web/20120620073511/http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6281_OpenSource.pdf

Update by Stefan 2022-08-23:
- Fix compilation error for ds109

Fixes: 8ac303d49f89 ("arm: kirkwood: Do not overwrite CONFIG_SYS_TCLK")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agotime: move the CONFIG_SYS_TIMER_RATE handling to the compiler
Michael Walle [Wed, 17 Aug 2022 19:37:48 +0000 (21:37 +0200)]
time: move the CONFIG_SYS_TIMER_RATE handling to the compiler

CONFIG_SYS_TIMER_RATE might be a dynamic value, i.e. a function call
instead of a static value, thus it has to be evaluated at runtime. If it
is a static value, the compiler should be able to optimize the unused
branches out.

This will be needed for kirkwoods dynamic CONFIG_SYS_TCLK setting.

Cc: Pali Rohár <pali@kernel.org>
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoarm: kirkwood: nsa310s: Add Distro boot capability
Tony Dinh [Thu, 11 Aug 2022 23:40:25 +0000 (16:40 -0700)]
arm: kirkwood: nsa310s: Add Distro boot capability

- Add distro boot to board include file and deconfig file
- Miscellaneous changes:
- Remove Gerald from maintainer list (email bounced)
- Add CONFIG_SUPPORT_PASSING_ATAGS and friends to support legacy
kernel method of booting (e.g. OpenWrt) with appended DTB.
- Add CONFIG_UBIFS_SILENCE_MSG to reduce binary size.

Note that this patch is depended on the following patch:
https://patchwork.ozlabs.org/project/uboot/patch/20220807192709.21717-1-pali@kernel.org/

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
2 years agoarm: mvebu: mbus: Fix mbus driver to work also after U-Boot relocation
Pali Rohár [Wed, 10 Aug 2022 12:46:09 +0000 (14:46 +0200)]
arm: mvebu: mbus: Fix mbus driver to work also after U-Boot relocation

mbus driver is initialized from arch_cpu_init() callback which is called
before relocation. This driver stores lot of functions and structure
pointers into global variables, so it is data position dependent.

Therefore after relocations all pointers are invalid and driver does not
work anymore as all pointers referes to the old memory, which overlaps with
CONFIG_SYS_LOAD_ADDR and ${loadaddr}.

For example U-Boot fuse command crashes if loadaddr memory is cleared or
rewritten by some image loaded by U-Boot load command.

  mw.w ${loadaddr} 0x0 10000
  fuse read 0 1 2

Fix this issue by removing of all mbus global variables in which are stored
pointers to structures or functions which changes during relocation. And
replace it by direct function calls (not via pointers). With this change
fuse command finally works.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Stefan Roese <sr@denx.de>