Tom Rini [Fri, 27 Oct 2023 19:23:21 +0000 (15:23 -0400)]
Merge tag 'efi-2024-01-rc2-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2024-01-rc2-2
Documentation:
* Bump urllib3 version
* Replace references to dm_dump_all() with dm_dump_tree()
* Update description of build dependencies for Alpine Linux
* Fix typo in gpt example
* Fix ordering of shell commands
Ilias Apalodimas [Thu, 19 Oct 2023 16:21:55 +0000 (11:21 -0500)]
efi_loader: fix EFI_ENTRY point on get_active_pcr_banks
efi_tcg2_get_active_pcr_banks doesn't immediately call the
EFI_ENTRY() wrapper once it enters the function. Move the call a
few lines above to cover the error cases properly as well.
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tom Fitzhenry [Tue, 24 Oct 2023 12:03:00 +0000 (23:03 +1100)]
doc: usage: fix ordering of shell commands
I initially didn't find the bootz docs when I went looking for them. :)
Signed-off-by: Tom Fitzhenry <tom@tom-fitzhenry.me.uk> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Dylan Corrales [Thu, 19 Oct 2023 14:02:30 +0000 (10:02 -0400)]
doc: Replace dm_dump_all() with dm_dump_tree()
Replace dm_dump_all() with dm_dump_tree() in driver model documentation,
to reflect changes introduced in commit 145287040480 ("dm: core: Rename
dm_dump_all()").
Tom Rini [Fri, 27 Oct 2023 14:19:17 +0000 (10:19 -0400)]
Merge tag 'u-boot-amlogic-20231027' of https://source.denx.de/u-boot/custodians/u-boot-amlogic
- Fix environment saving for new Android boot features on vim3*_android
- Add SPIFC support for Amlogic A1
- Add DFU RAM boot step when booting over USB
Igor Prusov [Tue, 24 Oct 2023 22:51:39 +0000 (01:51 +0300)]
spi: add support for Amlogic A1 SPI Flash Controller
Add A1 SPIFC driver from Linux. Slightly modified to use u-boot driver
framework and accommodate to lack of ioread32_rep/iowrite32_rep.
Based on Linux version 6.6-rc4
Signed-off-by: Igor Prusov <IVPrusov@sberdevices.ru> Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20231024225140.366571-2-ivprusov@sberdevices.ru Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
[trini: Drop <common.h> as it's not needed]
- kirkwood: Enable bootstd on some boards (Tony)
- mvebu: turris_mox: Extend to support RIPE Atlas Probe (Marek)
- mvebu/bubt: Support eMMC data partition booting (Josua)
Neil Armstrong [Mon, 23 Oct 2023 12:41:36 +0000 (14:41 +0200)]
configs: meson64: add alternate USB DFU boot target
Add boot over DFU RAM as an alternate to running script at
a fixed address like done today.
The main culprit is that it's not possible to do that
on G12A/Sm1 platforms due to changes in the USB boot protocol.
With this, U-Boot will present a DFU device with a ram slot where
the Host could write a fitImage or legacy U-Boot image, then with the
detach command boot will continue trying to boot the uploaded image.
The environment is used to configure some additional boot features such as:
* extra boot arguments
* enable AVB (Android Verified Boot) verification
Right now, we cannot store it in eMMC:
Loading Environment from nowhere... OK
Fix it by enabling the appropriate options in the defconfig
Fixes: b749d5ecdc06 ("configs: meson64_android: define raw parts for bootloader") Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231026-fix-saveenv-v1-1-6aa59be65481@baylibre.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Josua Mayer [Wed, 25 Oct 2023 08:22:54 +0000 (10:22 +0200)]
cmd: mvebu/bubt: move eMMC data-partition uboot from LBA-0 to 4096
A38x bootrom only searches 2 sectors when booting from eMMC,
irregardless of data or boot partition: 0 & 4096.
For eMMC boot partitions sector 0 is fine, but on data partition it
conflicts with MBR.
Change bubt command default to 4096 for eMMC data partition only, to
allow using an MBR partition table on the eMMC data partition while also
booting from it.
Signed-off-by: Josua Mayer <josua@solid-run.com> Reviewed-by: Stefan Roese <sr@denx.de>
Josua Mayer [Wed, 25 Oct 2023 08:22:53 +0000 (10:22 +0200)]
arm: mvebu: allow additional 4096 offset for bootable mmc image
Disarm the error message forcing u-boot/spl image to be located at
sector 0 on eMMC data-partition and microSD.
Offset 0 makes sense on eMMC boot partitions only, data partition must
use 4096 to avoid conflicting with MBR.
Valid offsets when booting from microSD, reported by boot-rom v1.73:
BootROM: Bad header at offset 00000200
BootROM: Bad header at offset 00004400
BootROM: Bad header at offset 00200000
BootROM: Bad header at offset 00400000
BootROM: Bad header at offset 00600000
BootROM: Bad header at offset 00800000
BootROM: Bad header at offset 00A00000
BootROM: Bad header at offset 00C00000
BootROM: Bad header at offset 00E00000
BootROM: Bad header at offset 01000000
BootROM: Bad header at offset 01200000
BootROM: Bad header at offset 01400000
BootROM: Bad header at offset 01600000
BootROM: Bad header at offset 01800000
BootROM: Bad header at offset 01A00000
BootROM: Bad header at offset 01C00000
BootROM: Bad header at offset 01E00000
BootROM: Bad header at offset 02000000
BootROM: Bad header at offset 02200000
BootROM: Bad header at offset 02400000
BootROM: Bad header at offset 02600000
BootROM: Bad header at offset 02800000
BootROM: Bad header at offset 02A00000
BootROM: Bad header at offset 02C00000
BootROM: Bad header at offset 02E00000
Valid offsets when booting from eMMC:
BootROM: Bad header at offset 00000000
BootROM: Bad header at offset 00200000
Switching BootPartitions.
BootROM: Bad header at offset 00000000
BootROM: Bad header at offset 00200000
Fixes: 2226ca17348 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header") Signed-off-by: Josua Mayer <josua@solid-run.com> Reviewed-by: Stefan Roese <sr@denx.de>
Milan P. Stanić [Tue, 17 Oct 2023 19:46:58 +0000 (21:46 +0200)]
doc: build: update description of build dependencies for Alpine Linux
Signed-off-by: Milan P. Stanić <mps@arvanta.net> Reviewed-by: Simon Glass <sjg@chromium.org>
Reformat and keep ncurses-dev needed for 'make menuconfig' Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
- Remove common.h in a number of places and make checkpatch.pl complain
about its use in all cases, allow the mbr command to handle 4 primary
partitions, fix an issue with the pstore command, fix a problem with
cli parsing of escape sequences, remove and ignore more files, allow
for the serial port to be flushed with every print (for debugging),
and add SCMI power domain support.
Rasmus Villemoes [Mon, 16 Oct 2023 08:35:22 +0000 (10:35 +0200)]
serial: introduce CONFIG_CONSOLE_FLUSH_ON_NEWLINE
When debugging, one sometimes only gets partial output lines or
nothing at all from the last printf, because the uart has a largish
buffer, and the code after the printf() may cause the CPU to hang
before the uart IP has time to actually emit all the characters. That
can be very confusing, because one doesn't then know exactly where the
hang happens.
Introduce a config knob allowing one to wait for the uart fifo to
drain whenever a newline character is printed, roughly corresponding
to the effect of setvbuf(..., _IOLBF, ...) in ordinary C programs.
Since this uses IS_ENABLED() instead of cpp ifdef, we can remove the
ifdef around the _serial_flush() definition - if neither
CONSOLE_FLUSH_SUPPORT or CONSOLE_FLUSH_ON_NEWLINE are enabled, the
compiler elides _serial_flush(), but it won't warn about it being
unused.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Simon Glass <sjg@chromium.org>
AKASHI Takahiro [Mon, 16 Oct 2023 05:39:43 +0000 (14:39 +0900)]
firmware: scmi: add power domain protocol support
In this patch, added are helper functions to directly manipulate
SCMI power domain management protocol. DM compliant power domain
driver will be implemented on top of those interfaces in a succeeding
patch.
cmd: mbr: Allow 4 MBR partitions without need for extended
Current code allows up to 3 MBR partitions without extended one.
If more than 3 partitions are required, then extended partition(s)
must be used.
This commit allows up to 4 primary MBR partitions without the
need for extended partition.
Add mbr test unit. In order to run the test manually, mmc6.img file
of size 12 MiB or greater is required in the same directory as u-boot.
Test also runs automatically via ./test/py/test.py tool.
Running mbr test is only supported in sandbox mode.
Signed-off-by: Alex Gendin <agendin@matrox.com>
[ And due to some further changes for testing ] Signed-off-by: Simon Glass <sjg@chromium.org>
But with these default address-cells and size-cells values, pstore
isn't working on A64. Root node for A64 defines 'address-cells' and
'size-cells' as 1.
dtc complains if reserved-memory has different address-cells and
size-cells.
```
Warning (ranges_format): /reserved-memory:ranges: empty "ranges"
property but its #address-cells (2) differs from / (1)
```
This patch takes into account address-cells and size-cells of the root
node and uses them as values for new reserved-memory node.
John Clark [Fri, 13 Oct 2023 13:26:16 +0000 (13:26 +0000)]
.gitignore: ignore misc include, simple-bin, and tools/generated build artifacts
make rock5b-rk3588_defconfig
make
git status
before
~~~~~~~
On branch master
Your branch is ahead of 'origin/master' by 1 commit.
(use "git push" to publish your local commits)
Untracked files:
(use "git add <file>..." to include in what will be committed)
include/autoconf.mk
include/autoconf.mk.dep
include/config.h
mkimage-in-simple-bin-spi.mkimage-rockchip-tpl
mkimage-in-simple-bin-spi.mkimage-u-boot-spl
mkimage-in-simple-bin.mkimage-rockchip-tpl
mkimage-in-simple-bin.mkimage-u-boot-spl
simple-bin-spi.map
simple-bin.fit.fit
simple-bin.fit.itb
simple-bin.map
tools/generated/
after
~~~~~~~
On branch master
Your branch is ahead of 'origin/master' by 1 commit.
(use "git push" to publish your local commits)
nothing to commit, working tree clean
Signed-off-by: John Clark <inindev@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
John Clark [Fri, 13 Oct 2023 13:23:07 +0000 (13:23 +0000)]
Makefile: remove misc include and simple-bin build artifacts on clean
make rock5b-rk3588_defconfig
make
make clean
git status
before
~~~~~~~
On branch master
Your branch is up to date with 'origin/master'.
Untracked files:
(use "git add <file>..." to include in what will be committed)
include/autoconf.mk
include/autoconf.mk.dep
include/config.h
mkimage-in-simple-bin-spi.mkimage-rockchip-tpl
mkimage-in-simple-bin-spi.mkimage-u-boot-spl
mkimage-in-simple-bin.mkimage-rockchip-tpl
mkimage-in-simple-bin.mkimage-u-boot-spl
simple-bin.fit.fit
simple-bin.fit.itb
after
~~~~~~~
On branch master
Your branch is ahead of 'origin/master' by 1 commit.
(use "git push" to publish your local commits)
Tom Rini [Thu, 12 Oct 2023 23:03:54 +0000 (19:03 -0400)]
include: Add <linux/types.h> in a few places
These files references a number of types that are defined in
<linux/types.h> (and so forth), so include it here rather than rely on
indirect inclusion.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Yurii Monakov [Tue, 10 Oct 2023 08:16:39 +0000 (11:16 +0300)]
cli: Consume invalid escape sequences early
Unexpected 'Esc' key presses are accumulated internally, even if it is
already clear that the current escape sequence is invalid. This results
in weird behaviour. For example, the next character after 'Esc' key
simply disappears from input and 'Unknown command' is printed
after 'Enter'.
This commit fixes some issues with extra 'Esc' keys entered by user:
1. Sequence <Esc><Esc><Enter> right after autoboot stop gives:
=>
nknown command 'ry 'help'
=>
2. Sequence <Esc><p><r><i><Enter> gives:
=> ri
Unknown command 'ri' - try 'help'
=>
3. Extra 'Esc' key presses break backspace functionality.
Signed-off-by: Yurii Monakov <monakov.y@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Tue, 24 Oct 2023 13:39:52 +0000 (09:39 -0400)]
Merge tag 'u-boot-rockchip-20231024' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add Board: rk3588 NanoPC-T6, Orange Pi 5, Orange Pi 5 Plus;
- clk driver fix for rk3568 and rk3588;
- rkmtd cmd support for rockchip nand device;
- dts update and sync from linux;
Johan Jonker [Wed, 18 Oct 2023 14:01:59 +0000 (16:01 +0200)]
rockchip: test: dm: add rkmtd test
Add Rockchip rkmtd test:
Create/attach/detach RKMTD device.
Send/read data with Rockchip boot block header.
Test that reusing the same label should work.
Basic test of 'rkmtd' commands.
Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Johan Jonker [Wed, 18 Oct 2023 14:01:40 +0000 (16:01 +0200)]
rockchip: cmd: add rkmtd command
The command rkmtd creates a virtual block device to transfer
Rockchip boot block data to and from NAND with block orientated
tools like "ums" and "rockusb".
It uses the Rockchip MTD driver to scan for boot blocks and copies
data from the first block in a GPT formated virtual disk.
Data must be written in U-boot "idbloader.img" format and start at
partition "loader1" offset 64. The data header is parsed
for length and offset. When the last sector is received
it erases up to 5 erase blocks on NAND and writes bootblocks
in a pattern depending on the NAND ID. Data is then verified.
When a block turns out bad the block header is discarded.
Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Johan Jonker [Wed, 18 Oct 2023 14:00:56 +0000 (16:00 +0200)]
rockchip: block: add rkmtd class and drivers
Add rkmtd class and drivers to create a virtual block device
to transfer Rockchip boot block data to and from NAND with
block orientated tools like "ums" and "rockusb".
Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
On Rockchip SoCs the first boot stages are written on NAND
with help of manufacturer software that uses a different format
then the MTD framework. Skip the automatic BBT scan with the
NAND_SKIP_BBTSCAN option to be able to pass the driver probe
function and to let the original data unchanged.
Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 17 Oct 2023 21:40:22 +0000 (21:40 +0000)]
board: rockchip: Add Xunlong Orange Pi 5 Plus
Xunlong Orange Pi 5 Plus is a single-board computer based on the
Rockchip RK3588 SoC. The board provides abundant interfaces, including
two HDMI output ports, one HDMI input port, two 2.5G Ethernet ports,
M.2 M-Key slot, M.2 E-Key slot, two USB 3.0, two USB 2.0, and two Type-C.
Features tested on a Orange Pi 5 Plus 4GB v1.2:
- SD-card boot
- eMMC boot
- SPI Flash boot
- PCIe/NVMe
- USB 2.0 host
- Ethernet
Device tree is imported from linux v6.7-rockchip-dts64-1 tag.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 17 Oct 2023 21:40:21 +0000 (21:40 +0000)]
board: rockchip: Add Xunlong Orange Pi 5
Xunlong Orange Pi 5 is a single-board computer based on the Rockchip
RK3588S SoC. The board provides abundant interfaces, HDMI output, GPIO
interface, M.2 PCIe2.0, Type-C, Gigabit LAN port, 2*USB2.0, 1*USB3.0,
etc.
Features tested on a Orange Pi 5 4GB v1.2:
- SD-card boot
- SPI Flash boot
- PCIe/NVMe
- USB 2.0 host
- Ethernet
Device tree is imported from linux v6.7-rockchip-dts64-1 tag.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 17 Oct 2023 17:02:11 +0000 (17:02 +0000)]
rockchip: rk3588-rock-5b: Sync USB3 nodes from mainline linux patches
The device tree for rk3588 and rock-5b contain usb3 nodes that have
deviated too much from current state of submitted mainline linux usb3
patches, see [1].
Sync usb3 related nodes from latest patches and collaboras rk3588 tree
so that dwc3-generic driver can be updated to include support for the
rockchip,rk3588-dwc3 compatible in the future, use rockchip,rk3568-dwc3
compatible until final node is merged in linux maintainer tree.
Jonas Karlman [Tue, 17 Oct 2023 17:02:10 +0000 (17:02 +0000)]
rockchip: rk3588-rock-5b: Enable support for PCIe SATA cards
Enable support for PCIe SATA cards and the on-board SATA controller.
This also revert use of CONFIG_PCI_INIT_R in order to speed up boot from
eMMC or SD-cards. Standard boot will initialize pci after faster boot
media have been enumerated.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Christopher Obbard <chris.obbard@collabora.com> Tested-by: Christopher Obbard <chris.obbard@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 17 Oct 2023 17:02:08 +0000 (17:02 +0000)]
rockchip: rk3588: Sync device tree from v6.7-rockchip-dts64-1 tag
Sync rk3588 device tree from v6.7-rockchip-dts64-1 tag.
Adds PCIe, button and led nodes to rk3588-evb1-v10 and rk3588-rock-5b
boards. Also remove includes from u-boot.dtsi-files that is no longer
needed.
Linux commits: 42145b7a8235 ("arm64: dts: rockchip: add PCIe network controller to rock-5b") 199cbd5f195a ("arm64: dts: rockchip: add PCIe for M.2 M-key to rock-5b") da447ec38780 ("arm64: dts: rockchip: add PCIe for M.2 E-Key to rock-5b") 86a2024d95e2 ("arm64: dts: rockchip: add PCIe2 network controller to rk3588-evb1") 46bb398ea1d8 ("arm64: dts: rockchip: add PCIe3 bus to rk3588-evb1") 1c9a53ff7ece ("arm64: dts: rockchip: Add sdio node to rock-5b") 3eaf2abd11aa ("arm64: dts: rockchip: Add sfc node to rk3588s") bf012368bb0a ("arm64: dts: rockchip: Add I2S2 M0 pin definitions to rk3588s") 3d77a3e51b0f ("arm64: dts: rockchip: Add UART9 M0 pin definitions to rk3588s") 0002c377e862 ("arm64: dts: rockchip: Remove duplicate regulator vcc3v3_wf from rock-5b") a6169ab36923 ("arm64: dts: rockchip: Enable UART6 on rock-5b") dd6dc0c4c126 ("arm64: dts: rockchip: Add AV1 decoder node to rk3588s") afa933c208e5 ("arm64: dts: rockchip: add ADC buttons to rk3588-evb1") 7952cbbda301 ("arm64: dts: rockchip: add status LED to rock-5b")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Christopher Obbard <chris.obbard@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Simon Glass [Mon, 23 Oct 2023 07:02:13 +0000 (00:02 -0700)]
bootstd: Scan all bootdevs in a boot_targets entry (take 2)
When the boot_targets environment variable is used with the distro-boot
scripts, each device is included individually. For example, if there
are three mmc devices, then we will have something like:
boot_targets="mmc0 mmc1 mmc2"
In contrast, standard boot supports specifying just the uclass, i.e.:
boot_targets="mmc"
The intention is that this should scan all MMC devices, but in fact it
currently only scans the first.
Update the logic to handle this case, without required BOOTSTD_FULL to
be enabled.
Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Date Huang <tjjh89017@hotmail.com> Reported-by: Vincent Stehlé <vincent.stehle@arm.com> Reported-by: Ivan Ivanov <ivan.ivanov@suse.com> Tested-by: Ivan T.Ivanov <iivanov@suse.de>
Simon Glass [Mon, 23 Oct 2023 07:02:12 +0000 (00:02 -0700)]
bootstd: Correct logic for single uclass
The current logic for "bootflow mmc" is flawed since it checks the
uclass of the bootdev instead of its parent, the media device. Correct
this and add a test that covers this scenario.
Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ivan T.Ivanov <iivanov@suse.de>
Simon Glass [Mon, 23 Oct 2023 07:02:10 +0000 (00:02 -0700)]
Revert "bootstd: Scan all bootdevs in a boot_targets entry"
This commit was intended to allow all bootdevs in each boot_targets
entry to be scanned. However it causes bad ordering with bootdevs, e.g.
scanning Ethernet bootdevs when it should be keeping to mmc.
Tom Rini [Mon, 23 Oct 2023 13:04:55 +0000 (09:04 -0400)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
This is mostly about support for the Allwinner R528/T113s SoC, which is
reportedly the same die as the Allwinner D1, but with the two
Arm Cortex-A7 cores activated instead of the RISC-V one.
Using sunxi code outside of arch/arm proved to be difficult, so apart
from enabling this Arm SoC, the patches also prepare for more refactoring
to get the D1 nicely supported some day:
- We get rid of some Kconfig (hard-)coded GPIO pins, responsible for
enabling regulators.
- The GPIO code is moved out of arch/arm, into drivers/gpio.
- Some definitions are moved out of header files under asm/arch.
- Some T113s/D1 specific definitions are guarded by a generic Kconfig
symbol (CONFIG_SUNXI_GEN_NCAT2).
- The DRAM controller initialisation code is located under drivers/ram.
- The base SoC .dtsi files are shared (under arch/riscv, as in Linux).
Of course there are also the usual new SoC specific patches, like clock
and pinmux descriptions, alongside a rework of the pinctrl code, since
Allwinner changed the GPIO register layout, for the first time since
sunxi's inception.
On top of this the PSCI code sees some update, to provide SMP services
for R528/T113s boards. Many thanks to Sam for providing this code and
staying strong through the review cycles.
The final patch enables support for one popular board, I hope to see
more DTs and defconfigs contributed in the future!
Many thanks to all the various contributors, testers and reviewers,
that series was a real team effort!
Artur Rojek [Wed, 18 Oct 2023 14:00:59 +0000 (16:00 +0200)]
board: Add support for Conclusive KSTR-SAMA5D27
Introduce support for Conclusive KSTR-SAMA5D27 Single Board Computer.
Co-developed-by: Jakub Klama <jakub@conclusive.pl> Signed-off-by: Jakub Klama <jakub@conclusive.pl> Co-developed-by: Marcin Jabrzyk <marcin@conclusive.pl> Signed-off-by: Marcin Jabrzyk <marcin@conclusive.pl> Signed-off-by: Artur Rojek <artur@conclusive.pl>
Artur Rojek [Wed, 18 Oct 2023 14:00:57 +0000 (16:00 +0200)]
event: add new EVT_SETTINGS_R event
Introduce EVT_SETTINGS_R, triggered post-relocation and before console
init.
This event gives an option to perform any platform-dependent setup,
which needs to take place before show_board_info(). Usage examples
include readout of EEPROM stored settings.
Signed-off-by: Artur Rojek <artur@conclusive.pl> Reviewed-by: Simon Glass <sjg@chromium.org>
Elaine Zhang [Thu, 12 Oct 2023 10:18:28 +0000 (18:18 +0800)]
clk: rockchip: rk3588: fix up the frac pll calculation
rk3588 frac pll:
FFVCO = ((m + k / 65536) * FFIN) / p
FFOUT = ((m + k / 65536) * FFIN) / (p * 2s)
k is the original code, but the K[15:0] is complement code
(6'b1000_0000_0000_0000 <= K[15:0] <= 16'b0111_1111_1111_1111),
need to be converted.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Sam Edwards [Thu, 12 Oct 2023 01:47:56 +0000 (19:47 -0600)]
sunxi: psci: implement PSCI on R528
This patch adds the necessary code to make nonsec booting and PSCI
secondary core management functional on the R528/T113.
Signed-off-by: Sam Edwards <CFSworks@gmail.com> Tested-by: Maksim Kiselev <bigunclemax@gmail.com> Tested-by: Kevin Amadiva <kevin.amadiva@mec.at> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Sam Edwards [Thu, 12 Oct 2023 01:47:55 +0000 (19:47 -0600)]
sunxi: psci: stop modeling register layout with C structs
Since the sunxi support nowadays generally prefers #defined register
offsets instead of modeling register layouts using C structs, now is a
good time to do this for PSCI as well. This patch moves away from using
the structs `sunxi_cpucfg_reg` and `sunxi_prcm_reg` in psci.c.
The former struct and its associated header file existed only to support
PSCI code, so also delete them altogether.
Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Sam Edwards [Thu, 12 Oct 2023 01:47:54 +0000 (19:47 -0600)]
sunxi: psci: refactor register access to separate functions
This is to prepare for R528, which does not have the typical
"CPUCFG" block; it has a "CPUX" block which provides these
same functions but is organized differently.
Moving the hardware-access bits to their own functions separates the
logic from the hardware so we can reuse the same logic.
Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Sam Edwards [Thu, 12 Oct 2023 01:47:53 +0000 (19:47 -0600)]
sunxi: psci: clean away preprocessor macros
This patch restructures psci.c to get away from the "many different
function definitions switched by #ifdef" paradigm to the preferred style
of having a single function definition with `if (IS_ENABLED(...))` to
make the optimizer include only the appropriate function bodies instead.
There are no functional changes here.
Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 2 Jul 2022 23:14:24 +0000 (00:14 +0100)]
sunxi: refactor serial base addresses to avoid asm/arch/cpu.h
At the moment we have each SoC's memory map defined in its own cpu.h,
which is included in include/configs/sunxi_common.h. This will be a
problem with the introduction of Allwinner RISC-V support.
Remove the inclusion of that header file from the common config header,
instead move the required serial base addresses (for the SPL) into a
separate header file. Then include the original cpu.h file only where
we really need it, which is only under arch/arm now.
This disentangles the architecture specific header files from the
generic code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Tue, 6 Sep 2022 14:59:57 +0000 (15:59 +0100)]
sunxi: add Allwinner R528/T113 SoC support
This adds the remaining code bits to teach U-Boot about Allwinner's
newest SoC generation. This was introduced with the RISC-V based
Allwinner D1 SoC, which actually shares a die with the ARM cores versions
called R528 (BGA, without DRAM) and T113s (QFP, with embedded DRAM).
This adds the new Kconfig stanza, using the two newly introduced symbols
for the new SoC generation and pincontroller. It also adds the new symbols
to the relavent code places, to set all the hardcoded bits directly.
We need one DT override:
The ARM core version of the DT specifies the CPUX watchdog as
"reserved", which means it won't be recognised by U-Boot. Override this
in our generic sunxi-u-boot.dtsi, to let U-Boot pick up this watchdog,
so that the generic reset driver will work.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 31 Dec 2022 18:38:21 +0000 (18:38 +0000)]
sunxi: add R528/T113-s3/D1(s) DRAM initialisation code
The Allwinner R528/T113-s/D1/D1s SoCs all share the same die, so use the
same DRAM initialisation code.
Make use of prior art here and lift some code from awboot[1], which
carried init code based on earlier decompilation efforts, but with a
GPL2 license tag.
This code has been heavily reworked and cleaned up, to match previous
DRAM routines for other SoCs, and also to be closer to U-Boot's coding
style and support routines.
The actual DRAM chip timing parameters are included in the main file,
since they cover all DRAM types, and are protected by a new Kconfig
CONFIG_SUNXI_DRAM_TYPE symbol, which allows the compiler to pick only
the relevant settings, at build time.
The relevant DRAM chips/board specific configuration parameters are
delivered via Kconfig, so this code here should work for all supported
SoCs and DRAM chips combinations.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Sam Edwards <CFSworks@gmail.com>
Andre Przywara [Sun, 18 Dec 2022 00:12:07 +0000 (00:12 +0000)]
Kconfig: sunxi: prepare for using drivers/ram/sunxi
At the moment all Allwinner DRAM initialisation routines are stored in
arch/arm/mach-sunxi, even though those "drivers" are just a giant
collection of writel's, without any architectural dependency.
The R528/T113-s SoC (with ARM cores) and the D1/D1s Soc (with RISC-V
cores) share the same die, so should share the same DRAM init routines as
well.
To prepare for this, add a new sunxi directory inside drivers/ram, and
add some stub entries to prepare for the addition of the share DRAM code
for those SoCs.
The RISC-V D1(s) SoCs will probably use SPL_DM, so for that SoC this
would be the right directory anyway.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sun, 1 May 2022 03:38:37 +0000 (22:38 -0500)]
clk: sunxi: Add support for the D1 CCU
Since the D1 CCU binding is defined, we can add support for its
gates/resets, following the pattern of the existing drivers.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Apart from using the new pinctrl MMIO register layout, the Allwinner D1
and related SoCs still need to usual set of mux values hardcoded in
U-Boot's pinctrl driver.
Add the values we need so far to this list, so that DM based drivers
will just work without further ado.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
projects / u-boot.git / log
