Haiying Wang [Wed, 28 Sep 2011 14:51:15 +0000 (10:51 -0400)]
powerpc/p5020: fixup portal config info
P5020 has 10 qman portals, we need to configure all of them:
* As there are only 2 physical cores sdest can only be 0 or 1
* We assign dqrr & frame data LIODNs for all portals so if they
are utilized the proper mapping tables can be setup uniquely
(PAMU stashing)
* We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN
assignments are tuned around an assumption of at most 5
partitions.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Wolfgang Denk [Wed, 12 Oct 2011 20:45:30 +0000 (22:45 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
* 'master' of git://git.denx.de/u-boot-ppc4xx:
ppc4xx: Change DDR2 CL from 4 to 5 for intip
ppc4xx: Improve lm63 pwm on dlvision-10g
ppc4xx: Do not stop booting on any keypress on intip
Wolfgang Denk [Wed, 12 Oct 2011 20:42:28 +0000 (22:42 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-microblaze
* 'master' of git://git.denx.de/u-boot-microblaze:
microblaze: Copy bootfile from variables
microblaze: Fix unaligned.h for endians
microblaze: Initialize jumptable and console
microblaze: Support flashes on lower addresses
microblaze: Call common console_init_f initialization function
This Jz4740-based clamshell device does not use NOR flash to boot.
The initial bring-up assumes that U-Boot is directly loaded into SDRAM
using USB boot tool, and starts from 0x80100000.
About USB boot tool
-------------------
Jz4740 is one of the XBurst processors with USB boot functionality
supported. The CPU can boot from a small ROM in the LSI, initialize
CPU and USB module, then wait for USB commands from the USB host.
We can send 8 KB binary data to the CPU cache using USB boot tool.
USB boot tool is available to the public at Ingenic website. Also
there is an alternative Debian package named xburst-tools.
Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net> Acked-by: Daniel <zpxu@ingenic.cn> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
Xiangfu Liu [Wed, 12 Oct 2011 04:24:06 +0000 (12:24 +0800)]
MIPS: Jz4740: Add NAND driver
Jz4740 NAND flash controller can support:
* MLC NAND as well as SLC NAND
* all 8-bit/16-bit NAND flash devices
* HAMMING and RS hardware ECC
* automatic boot up from NAND flash devices
nand_ecclayout is set up for 2GiB NAND chip mounted in Qi LB60.
We'll bring up boot-from-NAND support in nand_spl/ in the future.
Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net> Acked-by: Daniel <zpxu@ingenic.cn> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
Holger Brunck [Mon, 10 Oct 2011 11:08:19 +0000 (13:08 +0200)]
UBI: init eba tables before wl when attaching a device
This fixes that u-boot gets stuck when a bitflip was detected
during "ubi part <ubi_device>". If a bitflip was detected UBI tries
to copy the PEB to a different place. This needs that the eba table
are initialized, but this was done after the wear levelling worker
detects the bitflip. So changes the initialisation of these two
tasks in u-boot.
This is a u-boot specific patch and not needed in the linux layer,
because due to commit 1b1f9a9d00447d
UBI: Ensure that "background thread" operations are really executed
we schedule these tasks in place and not as in linux after the inital
task which schedule this new task is finished.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Lars Poeschel [Wed, 12 Oct 2011 09:31:19 +0000 (11:31 +0200)]
ubifs bad superblock bug
This patch fixes an issue when ubifs reads a bad superblock. Later it
tries to free memory, that was not allocated, which freezes u-boot.
This is fixed by looking for a non null pointer before free.
The message I got before u-boot freezes:
UBI: max/mean erase counter: 53/32
UBIFS: mounted UBI device 0, volume 1, name "rootfs"
UBIFS: mounted read-only
UBIFS: file system size: 49140 bytes (50319360 KiB, 0 MiB, 49140 LEBs)
UBIFS: journal size: 49 bytes (6838272 KiB, 0 MiB, 6678 LEBs)
UBIFS: media format: w4/r0 (latest is w4/r0)
UBIFS: default compressor: LZO
UBIFS: reserved for root: 0 bytes (0 KiB)
UBIFS error (pid 0): ubifs_read_node: bad node type (255 but expected 9)
UBIFS error (pid 0): ubifs_read_node: bad node at LEB 330:13104
UBIFS error (pid 0): ubifs_iget: failed to read inode 1, error -22
Error reading superblock on volume 'ubi:rootfs'!
Signed-off-by: Lars Poeschel <larsi@wh2.tu-dresden.de> Cc: Kyungmin Park <kmpark@infradead.org> Signed-off-by: Stefan Roese <sr@denx.de>
In nand_davinci_readecc(), select the correct NANDF<n>ECC register based
on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC.
This allows 1-bit hardware ECC to work with chip select other than CS2.
Note this now matches the usage in nand_davinci_enable_hwecc(), which
already had the correct handling, and allows refactoring to a single
function encapsulating the register read.
Without this fix, writing NAND pages to a chip not wired to CS2 would
result in in the ECC calculation always returning FFFFFF for each
512-byte segment, and reading back a correctly written page (one with
ECC intact) would always fail. With this fix, the ECC is written and
verified correctly.
Signed-off-by: Laurence Withers <lwithers@guralp.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Xiangfu Liu [Wed, 12 Oct 2011 04:24:06 +0000 (12:24 +0800)]
MIPS: Ingenic XBurst Jz4740 processor support
Jz4740 is a multimedia application processor targeting for mobile
devices like e-Dictionary, eBook, portable media player (PMP) and
GPS navigator. Jz4740 is powered by Ingenic 360 MHz XBurst CPU core
(JzRISC), in which RISC/SIMD/DSP hybrid instruction set architecture
provides high integration, high performance and low power consumption.
JzRISC incorporated in Jz4740 is the advanced and power-efficient
32-bit RISC core, compatible with MIPS32, with 16K I-Cache and 16K
D-Cache, and can operate at speeds up to 400 MHz.
On-chip modules such as LCD controller, embedded audio codec, multi-
channel SAR-ADC, AC97/I2S controller and camera I/F offer a rich
suite of peripherals for multimedia application. NAND controller
(SLC/MLC), USB (host 1.1 and device 2.0), UART, I2C, SPI, etc. are
also available.
For more info about Ingenic XBurst Jz4740:
http://en.ingenic.cn/eng/
http://www.linux-mips.org/wiki/Ingenic
This patch introduces XBurst CPU support in U-Boot. It's compatible
with MIPS32, but requires a bit different cache maintenance, timer
routines, and boot mechanism using USB boot tool, so XBurst support
can go into a separate new home, cpu/xburst/.
Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net> Acked-by: Daniel <zpxu@ingenic.cn> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
Xie Xiaobo [Mon, 3 Oct 2011 19:54:21 +0000 (12:54 -0700)]
powerpc/mpc8536ds: Save the env variables to SDcard and SPI flash
MPC8536DS offer booting from SDcard or SPI flash. This patch defined that
u-boot can save the environment variables on SDcard or SPI flash when
booting from the related device. The Env parameter region and linux
kernel region have overlap in SPI-Flash, So change the Env param saving
address.
Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Xie Xiaobo [Mon, 3 Oct 2011 19:18:40 +0000 (12:18 -0700)]
powerpc/mpc8536ds: Invert SDHC_WP pin polarity
MPC8536 Rev 1.0 silicon have NMG_eSDHC118 erratum, so that the SDHC write
protected pin polarity does not follow the SD card standard in MPC8536
Rev 1.0 silicon.
The MPC8536DS board invert the SDHC_WP pin as a workaround. However, this
silicon erratum has been fixed in Rev 1.1, So need invert the SDHC_WP
polarity again when use the MPC8536 Rev1.1 and greater on MPC8536DS board.
Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Xie Xiaobo [Mon, 3 Oct 2011 19:18:39 +0000 (12:18 -0700)]
powerpc/mpc8536ds: Add eSPI support for MPC8536DS
1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS,
so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width
to 4-bit and enable SPI signals.
2. Add eSPI controller and SPI-FLASH definition.
Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
- Increase the size of malloc space.
- Enable e1000 network card.
- Show pci devices on startup.
- Change the location of env address.
- Use hwconfig to turn off ECC by default.
[Kumar Gala] Fixed white space formating for CONFIG_EXTRA_ENV_SETTINGS
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Becky Bruce [Tue, 4 Oct 2011 00:10:51 +0000 (19:10 -0500)]
powerpc/mpc86xx: Disable translation for BAT setup
We really shouldn't be overwriting bat registers with translation enabled,
especially when we're executing code using one of them for translating
the current instruction stream. Instead, disable address translation
while doing the final BAT setup.
In order to do this, setup_bats has to move back to asm code, because we
require translation to be enabled to have a stack for C code. The yucky
thing about that is that the assembler doesn't like ULL so we have to
switch to using HIGH/LOW pairs for physical addresses that are > 32 bits
in length.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Timur Tabi [Tue, 4 Oct 2011 21:44:43 +0000 (16:44 -0500)]
powerpc/85xx: fix null pointer dereference when init the SGMII TBI PHY
Function dtsec_configure_serdes() needs to know where the TBI PHY registers
are in order to configure SGMII for proper SerDes operation.
During SGMII initialzation, fm_eth_init_mac() passing NULL for 'phyregs'
when it called init_dtsec(), because it was believed that phyregs was not
used. In fact, it is used by dtsec_configure_serdes() to configure the TBI
PHY registers.
We also need to define the PHY registers in struct fm_mdio.
Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Mon, 3 Oct 2011 16:19:53 +0000 (09:19 -0700)]
powerpc/mpc8xxx: Merge entries in DDR speed table
It is not necessary to keep multiple entries for the same setting in DDR
speed tables. Merge them for smaller tables. Also restructure the tables
for smaller size. Cleanup some typedefs.
Enforce strict checking for speed table. If DIMM is running at higher than
known speed, try to use the highest speed setting. If rank is unknown, it
has to panic.
Removed ODT overriding for P2020DS as it is not necessary.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Andy Fleming [Wed, 20 Apr 2011 23:41:17 +0000 (18:41 -0500)]
phylib: Work around bug in Teranetics PHY
The Teranetics PHY does not properly report the link state
for fiber connections. The new PHY code actually checked the link,
and so the FM driver would refuse to talk over a linkless PHY.
But the link may actually be up, so now we always report it as up
for fiber connections on the tn2020.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Timur Tabi [Tue, 6 Sep 2011 14:36:06 +0000 (09:36 -0500)]
powerpc/85xx: CONFIG_ENABLE_36BIT_PHYS does not depend on CONFIG_PHYS_64BIT
The macro CONFIG_ENABLE_36BIT_PHYS is used to indicate that the given SOC is
capable of 36-bit physical addresses, even if such large addresses are not
used. On two boards, this macro was enabled only when building a 36-bit
image.
Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Fri, 16 Sep 2011 20:21:35 +0000 (13:21 -0700)]
powerpc/8xxx: Add support for interactive DDR programming interface
Interactive DDR debugging provides a user interface to view and modify SPD,
DIMM parameters, board options and DDR controller registers before DDR is
initialized. With this feature, developers can fine-tune DDR for board
bringup and other debugging without frequently having to reprogram the flash.
To enable this feature, define CONFIG_FSL_DDR_INTERACTIVE in board header
file and set an environment variable to activate it. Syntax:
setenv ddr_interactive on
After reset, U-boot prompts before initializing DDR controllers
FSL DDR>
The available commands are
print print SPD and intermediate computed data
reset reboot machine
recompute reload SPD and options to default and recompute regs
edit modify spd, parameter, or option
compute recompute registers from current next_step to end
next_step shows current next_step
help this message
go program the memory controller and continue with u-boot
The first command should be "compute", which reads data from DIMM SPDs and
board options, performs the calculation then stops before setting DDR
controller. A user can use "print" and "edit" commands to view and modify
anything. "Go" picks up from current step with any modification and
compltes the calculation then enables the DDR controller to continue u-boot.
"Recompute" does it over from fresh reading.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Wolfgang Denk [Wed, 5 Oct 2011 21:11:19 +0000 (23:11 +0200)]
common/usb.c: fix warning: variable ... set but not used
Fix:
usb.c: In function 'usb_parse_config':
usb.c:331:17: warning: variable 'ch' set but not used [-Wunused-but-set-variable]
usb.c: In function 'usb_hub_port_connect_change':
usb.c:1123:29: warning: variable 'portchange' set but not used [-Wunused-but-set-variable]
usb.c: In function 'usb_hub_configure':
usb.c:1183:25: warning: variable 'hubsts' set but not used [-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Remy Bohmer <linux@bohmer.net> Acked-by: Remy Bohmer <linux@bohmer.net>
Wolfgang Denk [Wed, 5 Oct 2011 20:59:27 +0000 (22:59 +0200)]
drivers/net/smc91111.c: fix warning: variable ... set but not used
Fix:
smc91111.c: In function 'smc_phy_configure':
smc91111.c:1194:6: warning: variable 'failed' set but not used [-Wunused-but-set-variable]
smc91111.c:1190:7: warning: variable 'phyaddr' set but not used [-Wunused-but-set-variable]
Wolfgang Denk [Wed, 5 Oct 2011 20:58:11 +0000 (22:58 +0200)]
fs/jffs2/jffs2_1pass.c: fix warning: variable ... set but not used
Fix:
jffs2_1pass.c: In function 'jffs2_1pass_read_inode':
jffs2_1pass.c:699:7: warning: variable 'ret' set but not used [-Wunused-but-set-variable]
jffs2_1pass.c: In function 'jffs2_1pass_build_lists':
jffs2_1pass.c:1578:14: warning: variable 'empty_start' set but not used [-Wunused-but-set-variable]
Wolfgang Denk [Wed, 5 Oct 2011 20:48:12 +0000 (22:48 +0200)]
CFI: fix warning: variable ... set but not used
Fix:
cfi_mtd.c: In function 'cfi_mtd_init':
cfi_mtd.c:226:19: warning: variable 'mtd_list' set but not used [-Wunused-but-set-variable]
cfi_mtd.c: In function 'cfi_mtd_init':
cfi_mtd.c:225:6: warning: unused variable 'devices_found'
cfi_mtd.c: In function 'cfi_mtd_init':
cfi_mtd.c:226:19: warning: variable 'mtd_list' set but not used [-Wunused-but-set-variable]
[-Wunused-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Acked-by: Stefan Roese <sr@denx.de>
Wolfgang Denk [Fri, 7 Oct 2011 07:58:21 +0000 (09:58 +0200)]
README: fix documentation of CONFIG_SHOW_BOOT_PROGRESS
Some previous changes added code right in the middle of the
description of CONFIG_SHOW_BOOT_PROGRESS. Move this text down.
Fix formatting while we are at it.
Stefan Roese [Fri, 7 Oct 2011 01:05:49 +0000 (01:05 +0000)]
ppc: Fix DBSR_IAx defines in <bedbug/regs.h>
While adding asm/cache.h to common.h for PPC targets, I got an
error about multiple definitions of some DBSR_ macros. While
scanning these defines, I noticed that some where defined not
correctly for all PPC variants. So I removed all unused defines,
and corrected the ones really used by bedbug (book-e vs. ppc40x).
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de>
Stefan Roese [Fri, 7 Oct 2011 01:05:34 +0000 (01:05 +0000)]
ppc: Include <asm/cache.h> in common.h
This is needed for the patch "cache: add default setting for
CONFIG_SYS_CACHELINE_SIZE" from Anton Staaf. As cache.h defines
CONFIG_SYS_CACHELINE_SIZE for PPC targets.
This will remove the following warnings/errors:
include/common.h:819:2: warning: #warning CONFIG_SYS_CACHELINE_SIZE not defined, using __BIGGEST_ALIGNMENT__
cache.c:33: error: '__BIGGEST_ALIGNMENT__' undeclared (first use in this function)
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Anton Staaf <robotboy@chromium.org> Cc: Wolfgang Denk <wd@denx.de>
Loïc Minier [Mon, 3 Oct 2011 09:57:12 +0000 (11:57 +0200)]
ublimage: NAND block size isn't set at build-time
mkimage's ublimage support can't depend of build-time board configs;
instead, this should be set in ublimage.cfg. Since currently no configs
in u-boot override the NAND block size, hardcode it as such in
ublimage.h to fix a build failure with "make tools":
gcc [...] -o ublimage.o ublimage.c -c
In file included from ublimage.c:37:0:
ublimage.h:31:20: fatal error: config.h: No such file or directory
Loïc Minier [Mon, 3 Oct 2011 09:57:10 +0000 (11:57 +0200)]
Build timestamp_autogenerated.h without config
Tools such as mkimage include version information but are
config-agnostic; build timestamp_autogenerated.h even when config.mk
isn't generated to fix "make tools" build failure:
gcc [...] -o mkimage.o mkimage.c -c
In file included from include/version.h:27:0, from mkimage.c:26:
include/timestamp.h:27:37: fatal error: timestamp_autogenerated.h: No
such file or directory
Cc: patches@linaro.org Signed-off-by: Loïc Minier <loic.minier@linaro.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
Mike Frysinger [Sun, 2 Oct 2011 10:01:27 +0000 (10:01 +0000)]
net: drop !NET_MULTI code
This is long over due. All but two net drivers have been converted, but
those have now been dropped.
The only thing left to do is actually delete all references to NET_MULTI
and code that is compiled when that is not defined. So here we scrub the
core code.
Mike Frysinger [Sun, 2 Oct 2011 10:01:25 +0000 (10:01 +0000)]
net: drop !NET_MULTI bcm570x/tigon3 drivers
These drivers have never been converted to NET_MULTI, and they are only
used by one board (BMW). So drop the drivers until someone feels like
rewriting them for NET_MULTI support.
Rather than punting the BMW board completely, just disable net support
in its board config. Seems to build fine without it.
Now that we've got boards.cfg and most people have converted over,
start warning people who have yet to so we can phase board configs
completely out of the Makefile.
Mike Frysinger [Sun, 25 Sep 2011 19:27:19 +0000 (19:27 +0000)]
MAKEALL: rename coldfire list to m68k to match arch
The m68k tree is the only one where `./MAKEALL <arch>` does not work.
So rename the existing coldfire list in the MAKEALL script to m68k, and
add an alias from coldfire to m68k. This makes scripting around MAKEALL
easier.
Some images have not a header of fix lenght. The patch will be
used for the generation of AIS images, because this header has
a variable lenght. The patch adds also the parameter "-s" (skip)
to not copy automatically the passed image file.
This test is similar to the actual POST memory test but quicker and
far less complete. It checks the address and data lines and then only
tests some regularly placed sub regions of the RAM.
This can be useful when we want to test the RAM but we do not have enough
time to run the full memory test.
The POST memory test code was rearranged in order to avoid code duplication
between the two tests but the memory test functionnality remains the same.
Some boards have the environment variables defined in a slow EEPROM. post_run
accesses these environment variables to define which tests have to be run (in
post_get_flags). This is very slow before the code relocation on some boards
with a slow I2C EEPROM for environement variables.
This patch adds a config option to skip the fetching of the test flags in the
environment variables. The test flags assigned to the tests then only are the
ones statically defined for the test in post/tests.c.
POST: add post_log_res field for post results in global data
The current post_log_word in global data is currently split into 2x
16 bits: half for the test start, half for the test success.
Since we alredy have more than 16 POST tests defined and more could
be defined, this may result in an overflow and the post_output_backlog
would not work for the tests defined further of these 16 positions.
An additional field is added to global data so that we can now support up
to 32 (depending of architecture) tests. The post_log_word is only used
to record the start of the test and the new field post_log_res for the
test success (or failure). The post_output_backlog is for this change
also adapted.
The predefinde post_word_load/store functions do not fit all boards,
so we introduce a way to define post_word_load/store as externs in
post.h that then can be defined in board specific files. This is done
with the CONFIG_POST_EXTERNAL_WORD_FUNCS #define
Allow redirection of console output prior to console initialisation to a
temporary buffer.
To enable this functionality, the board (or arch) must define:
- CONFIG_PRE_CONSOLE_BUFFER - Enable pre-console buffer
- CONFIG_PRE_CON_BUF_ADDR - Base address of pre-console buffer
- CONFIG_PRE_CON_BUF_SZ - Size of pre-console buffer (in bytes)
The pre-console buffer will buffer the last CONFIG_PRE_CON_BUF_SZ bytes
Any earlier characters are silently dropped.
Wolfgang Denk [Wed, 5 Oct 2011 09:55:01 +0000 (09:55 +0000)]
TQM8xx: make room for growing code size due to I/O accessor cleanup
Commit "PPC: Cleanup tqm8xx_pcmcia.c" will clean up the PCMCIA code
to use I/O accessors instead of plain volatile pointer accesses.
This will result in about 300 byte bigger code. Fix custom linker
script to make room for this.
While we are at it, drop unmaintained u-boot.lds.debug linker script.
Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Tested-by: Wolfgang Denk <wd@denx.de>
Wolfgang Denk [Tue, 4 Oct 2011 20:20:25 +0000 (22:20 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
* 'master' of git://git.denx.de/u-boot-nand-flash:
PPC: Fix socrates NAND problem
PPC: Fix fsl_upm.c by renaming nand handling functions
NAND: Make page, erase, oob size available via cmd_nand
mtd: eLBC NAND: remove elbc_fcm_ctrl->oob_poi
NAND: Add -y option to nand scrub command
NAND: Add nand read.raw and write.raw commands
NAND: Really ignore bad blocks when scrubbing
spl, nand: add 4bit HW ecc oob first nand_read_page function
mxc_nand: fix a problem writing more than 32MB
mxc_nand: fixed some typos (cosmetic)
nand: increase chip_delay in mv kirkwood nand driver
Wolfgang Denk [Tue, 4 Oct 2011 20:08:13 +0000 (22:08 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
powerpc/p3060: Add SoC related support for P3060 platform
powerpc/85xx: Add support for setting up RAID engine liodns on P5020
powerpc/85xx: Refactor some defines out of corenet_ds.h
fm-eth: Add ability for board code to disable a port
powerpc/mpc8548: Add workaround for erratum NMG_LBC103
powerpc/mpc8548: Add workaround for erratum NMG_DDR120
powerpc/mpc85xxcds: Fix PCI speed
powerpc/mpc8548cds: Fix booting message
powerpc/p4080: Add support for secure boot flow
powerpc/85xx: Add Secure Boot support on P1010RDB for NOR, NAND & SPIFLASH
powerpc/85xx: Add PBL & SECUREBOOT support on P3041/P5020DS boards
powerpc/p2041rdb: remove watch dog related codes
powerpc/p2041rdb: updated description of cpld command
powerpc/p2041rdb: add more ddr frequencies support
powerpc/p2041rdb: set sysclk according to status of physical switch SW1
powerpc/p2041rdb: update cpld reset command according to CPLD 2.0
powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver
powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver
powerpc/mpc8xxx: Add DDR2 to unified DDR driver
powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps()
powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots
powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en
powerpc/85xx: Refactor P2041RDB to use common p_corenet files
powerpc/85xx: refactor common P-Series CoreNet files for FSL boards
powerpc/85xx: Enable CMD_REGINFO on corenet boards
powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries
powerpc/85xx: Fix USB protocol definitions for P1020RDB
powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM
powerpc/mpc8xxx: Move DDR RCW overriding to common code
powerpc/mpc8xxx: Extend CWL table
powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536
powerpc/85xx: Cleanup extern in corenet_ds board code
powerpc/p2041rdb: Add ethernet support on P2041RDB board
powerpc/85xx: Add networking support to P1023RDS
powerpc/hydra: Add ethernet support on P5020/P3041 DS boards
powerpc/85xx: Add FMan ethernet support to P4080DS
powerpc/85xx: Add support for FMan ethernet in Independent mode
powerpc/mpc8548cds: Cleanup mpc8548cds.c
powerpc/mp: add support for discontiguous cores
powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries
fdt: Add new fdt_create_phandle helper
fdt: Rename fdt_create_phandle to fdt_set_phandle
powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set
fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)
powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)
fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)
powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M
powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB
nand: Freescale Integrated Flash Controller NAND support
powerpc/85xx: Add basic support for P1010RDB
powerpc/85xx: Add support for new P102x/P2020 RDB style boards
powerpc/85xx: relocate CCSR before creating the initial RAM area
powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros
powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0
powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014
Wolfgang Denk [Tue, 4 Oct 2011 20:05:15 +0000 (22:05 +0200)]
Merge branch 'emaclite' of git://git.denx.de/u-boot-microblaze
* 'emaclite' of git://git.denx.de/u-boot-microblaze:
net: emaclite: Use dynamic allocation
net: emaclite: Remove baseaddress from xemaclite
net: emaclite: Use calloc instead of malloc
net: emaclite: Remove deviceid property
net: emaclite: Change driver name and add address
Wolfgang Denk [Tue, 4 Oct 2011 19:32:16 +0000 (21:32 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-microblaze
* 'master' of git://git.denx.de/u-boot-microblaze:
microblaze: Enable FDT/FIT support
microblaze: Remove address offset for uart16550
microblaze: Do not select NFS for platforms without ethernet
microblaze: Clean up reset asm code
microblaze: Save and restore first unused vector
microblaze: Setup MB vectors if feature is enable for u-boot
microblaze: Remove debug saving value
The commit causes build breakage for a number of boards. This results
from the fact that now the arguments of debug() actually get
referenced (even if there is hope that the compiler will optimize
away the debug() call). The obvious fix to that probem (change the
code to always declare the referenced variables and data structures)
increases the code size, and was this rejected. So it was decided to
revert this commit until a better solution is found.
Marek Vasut [Mon, 3 Oct 2011 22:56:09 +0000 (00:56 +0200)]
PPC: Fix socrates NAND problem
nand.c:36: error: static declaration of 'nand_read_buf' follows non-static declaration
/home/marex/u-boot/include/nand.h:139: error: previous declaration of 'nand_read_buf' was here
Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
The eLBC NAND driver currently follows up each program/write operation with a
read-back of the page, in order to [ostensibly] fill in ECC data for the
caller. However, the page address used for this read is always -1, so the read
will never work correctly. Remove this useless (and potentially problematic)
block of code.
v2: fix broken mailer
Signed-off-by: mhench <mhench@elutions.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Marek Vasut [Tue, 13 Sep 2011 22:20:35 +0000 (00:20 +0200)]
NAND: Add -y option to nand scrub command
This allows the scrub command to scrub without asking the user if he really
wants to scrub the area. Useful in scripts.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Acked-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
Marek Vasut [Fri, 23 Sep 2011 13:43:10 +0000 (15:43 +0200)]
NAND: Add nand read.raw and write.raw commands
These commands should work around various "hardware" ECC and BCH methods.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
[scottwood@freescale.com: s/write the page/access the page/] Signed-off-by: Scott Wood <scottwood@freescale.com>
Marek Vasut [Mon, 12 Sep 2011 04:04:06 +0000 (06:04 +0200)]
NAND: Really ignore bad blocks when scrubbing
Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
[scottwood@freescale.com: use chip instead of redundant priv_nand] Signed-off-by: Scott Wood <scottwood@freescale.com>
Helmut Raiger [Wed, 6 Jul 2011 17:04:41 +0000 (19:04 +0200)]
mxc_nand: fix a problem writing more than 32MB
When writing 0x4000 to the unlockend_blkaddr register, large writes to
a 2k page NAND sometimes fail. The current kernel driver writes 0xFFFF
to this register for V2 of the nand controller.
However on an i.MX31 this also fixes writes larger than 32MB.
The datasheet is very unspecific, but (0x4000=16384)*2000
roughly fits the limits we're encountering with NAND writes.
This problem might be NAND chip specific.
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> Signed-off-by: Scott Wood <scottwood@freescale.com>
Stefan Bigler [Mon, 18 Jul 2011 13:25:11 +0000 (15:25 +0200)]
nand: increase chip_delay in mv kirkwood nand driver
The new SAMSUNG NAND Flash K9F1G08U0D require a bigger chip_delay.
The Data Transfer from Cell to Register is >= 35us. Other Vendors
and older chips normally use >= 25us. To have enough margin 40us
is selected.
Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Stefan Roese <sr@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
Shengzhou Liu [Wed, 31 Aug 2011 09:48:18 +0000 (17:48 +0800)]
powerpc/p3060: Add SoC related support for P3060 platform
Add P3060 SoC specific information:cores setup, LIODN setup, etc
The P3060 SoC combines six e500mc Power Architecture processor cores with
high-performance datapath acceleration architecture(DPAA), CoreNet fabric
infrastructure, as well as network and peripheral interfaces.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Sat, 10 Sep 2011 15:44:13 +0000 (10:44 -0500)]
powerpc/85xx: Add support for setting up RAID engine liodns on P5020
Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each
Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2
Rings per JQ). This just handles RAID Engine in non-DPAA mode.
Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Wed, 31 Aug 2011 14:50:13 +0000 (09:50 -0500)]
powerpc/85xx: Refactor some defines out of corenet_ds.h
Move some SoC/board specific defines out of corenet_ds.h and into the
corresponding P3041DS/P4080DS/P5020.h.
We moved CONFIG_MMC, CONFIG_PCIE3, & CONFIG_FSL_NGPIXIS because the P3060
SoC/reference board does not have these devices and it will share the same
board code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
projects / u-boot.git / log
