Tom Rini [Tue, 19 Dec 2023 15:15:57 +0000 (10:15 -0500)]
Merge patch series "Fix J7200 kernel boot when using upstream u-boot"
Reid Tonking <reidt@ti.com> says:
Since the 09.01.00.002 release of ti-linux-firmware [0] upstream uboot
has led to the kernel hanging during boot [1] for the TI J7200 S0C. The
issue was found to be a few patches that had be added to ti-u-boot, but not
yet upstreamed. This series adds the missing two patches to allow upstream
u-boot to boot the kernel properly [2].
Bryan Brattlof [Thu, 7 Dec 2023 16:52:10 +0000 (10:52 -0600)]
arm: mach-k3: j72xx: add new 'virtual' mux
In order for the Cortex-A72s to operate at different frequencies other
than the default 2GHz, add in a new 'virtual' mux (a mux that does not
physically exist in the clock tree) that can be selected.
Julien Masson [Mon, 4 Dec 2023 10:48:55 +0000 (11:48 +0100)]
arm: mediatek: add support for MediaTek MT8365 SoC
This patch adds basic support for MediaTek MT8365 SoC.
The dtsi has been copied from Linux source code tag v6.7-rc2.
(commit 9b5d64654ea8f51fe1e8e29ca1777b620be8fb7c)
spl_mmc_emmc_boot_partition return a number different from 0
if the partition is a boot one. We can have the uboot img
for instance in a raw offset in emmc partition 0 so we would
like to continue to load the next stage. If the user want
to use EMMC as boot device allow him to use any part of the
emmc and not only boot partition
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Etienne Carriere [Wed, 29 Nov 2023 12:37:53 +0000 (13:37 +0100)]
tee: optee: don't enumerate services if there ain't any
Change optee driver service enumeration to not enumerate (and
allocate a zero sized shared memory buffer) when OP-TEE
reports that there is no service to enumerate.
This change fixes an existing issue that occurs when the such zero
sized shared memory buffer allocated from malloc() has a physical
address of offset 0 of a physical 4kB page. In such case, OP-TEE
secure world refuses to register the zero-sized shared memory
area and makes U-Boot optee service enumeration to fail.
Etienne Carriere [Wed, 29 Nov 2023 12:37:52 +0000 (13:37 +0100)]
tee: optee: don't fail on services enumeration failure
Change optee probe function to only warn when service enumeration
sequence fails instead of reporting an optee driver probe failure.
Indeed U-Boot can still use OP-TEE even if some OP-TEE services are
not discovered.
Udit Kumar [Sat, 25 Nov 2023 18:29:39 +0000 (23:59 +0530)]
remoteproc: k3-dsp: Avoid reloading of firmware
DSP core is going into abnormal state when load callback is called
after starting of DSP core.
Reload of firmware needs core to be stopped first, followed by
load.
So avoid loading of firmware, when core is started.
Robert Catherall [Thu, 23 Nov 2023 18:22:58 +0000 (18:22 +0000)]
arm: vexpress64: juno: Allow boot from VirtIO
The AEM and Juno FVPs (Fixed Virtual Platforms) support a VirtIO
disc interface. Adding VIRTIO to the list of boot devices allows
these FastModel platforms to boot from 'disc' in the same way
the hardware counterpart can boot from SATA or USB.
This is a NOP if CONFIG_CMD_VIRTIO is not enabled, so no impact
on Juno hardware (which is built with vexpress_aemv8a_juno_defconfig)
Signed-off-by: Robert Catherall <robert.catherall@arm.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Michal Simek [Mon, 6 Nov 2023 11:56:47 +0000 (12:56 +0100)]
riscv: Add support for AMD/Xilinx MicroBlaze V
MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
It is hardware compatible with classic MicroBlaze processor.
The patch contains initial wiring and configuration for initial HW design
with memory, cpu, interrupt controller, timers and uartlite console
(interrupt controller is listed but U-Boot is not using it).
Provided DT is just describing one configuration and should be taken only
as example.
Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Sean Anderson [Sat, 2 Dec 2023 19:33:14 +0000 (14:33 -0500)]
doc: Replace examples of MD5 and SHA1 with SHA256
Both SHA1 and (especially) MD5 are no longer as safe as they once were for
cryptographic use. Replaces examples which use them with examples using
SHA256 instead. This will provide more-secure defaults for users who use
documentation examples as a base for their own use. This is not too
necessary for non-verified-boot scenarios (since someone could just replace
the checksum), but I wanted to be complete.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
AKASHI Takahiro [Tue, 21 Nov 2023 01:29:44 +0000 (10:29 +0900)]
cmd: bootefi: move library interfaces under lib/efi_loader
In the prior commits, interfaces for executing EFI binary and boot manager
were carved out. Move them under efi_loader directory so that they can
be called from other places without depending on bootefi command.
Only efi_selftest-related code will be left in bootefi.c.
AKASHI Takahiro [Tue, 21 Nov 2023 01:29:43 +0000 (10:29 +0900)]
cmd: bootefi: localize global device paths for efi_selftest
Device paths allocated in bootefi_test_prepare() will be immediately
consumed by do_efi_selftest() and there is no need to keep them for later
use. Introduce test-specific varialbles to make it easier to move other
bootmgr functions into library directory in the next commit.
Andrew Davis [Thu, 30 Nov 2023 14:49:11 +0000 (08:49 -0600)]
board: ti: k3: Remove need for CFG_SYS_SDRAM_BASE
The base address of extended DDR does not change across the K3 family.
Setting this per SoC is not needed. Remove this definition to help
remove the last bits from K3 include/configs/*.h files.
Vishal Mahaveer [Tue, 28 Nov 2023 19:40:24 +0000 (13:40 -0600)]
board: ti: am62x/am62ax: Update virtual interrupt allocations in board config
Updates as a result of TIFS core now reserving a virtual interrupt
for enabling interrupts between DM to TIFS core. Because of this
change other virtual interrupt counts decrease by one.
Update am62ax rm-cfg with allocation entries for C7x core. Following
updates are added for C7x:
- Share split BCDMA tx and rx channels between DM R5 and C7x
- Share rings for split BCDMA tx and rx channels between DM R5 and C7x
- Add Global events and Virtual interrupts for C7x
Andrew Davis [Tue, 28 Nov 2023 17:05:27 +0000 (11:05 -0600)]
arm: mach-k3: Remove non-cached memory map areas
All normal memory areas should be mapped as such.
We added these un-cached holes in our memory map to hack around the
remoteproc driver missing the proper cache maintenance operations.
The problem is having these non-cached memory map areas causes stability
issues later in system operation due to the nature of the K3 coherency
architecture. Plus these are board specific carveouts and instead
should have been added at the board level, not here in the SoC common
code area.
Remove these non-cached memory map areas.
Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Tested-by: Nishanth Menon <nm@ti.com>
Andrew Davis [Tue, 28 Nov 2023 17:05:26 +0000 (11:05 -0600)]
arm: mach-k3: Do not map ATF and OPTEE regions in MMU
ATF and OPTEE regions may be firewalled from non-secure entities. To
prevent access to this area we leave a hole there in the MMU map. This
is the same idea as [0] but we complete that patch by adding the same
for AM65, J721e, J7200, and J721s2 here.
[0] commit 0688ff3ae23c ("arm: mach-k3: arm64-mmu: do not map ATF and OPTEE regions in A53 MMU")
Andrew Davis [Tue, 28 Nov 2023 17:05:25 +0000 (11:05 -0600)]
arm: mach-k3: Let the compiler size the mem_map lists
NR_MMU_REGIONS is a copy/paste from another platform that extends
this list later. We do not do that, so let the list be the size
of the initializer list.
Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Tested-by: Nishanth Menon <nm@ti.com>
Andrew Davis [Wed, 22 Nov 2023 21:30:05 +0000 (15:30 -0600)]
arm: mach-k3: Move K3 common schema.yaml out of board directory
This file is common for all K3, move it out of board/ directory and
into mach-k3. As we need to change the path in k3-binman.dtsi let's
take this opportunity to switch to absolute paths which makes adding
non-TI boards (like Toradex Verdin) not need to override these paths.
Tom Rini [Fri, 15 Dec 2023 18:33:11 +0000 (13:33 -0500)]
Merge tag 'u-boot-stm32-20231215' of https://source.denx.de/u-boot/custodians/u-boot-stm into next
_ run savedefconfig on all STM32 defconfig
STM32 MCU:
_ Sync stm32f469-disco DT with Linux 6.5
_ rework ltdc node for stm32f769-disco
_ clk: stm32f: Fix settings for LCD_CLK
_ Support display on stm32f469-disco board
Jim Liu [Tue, 14 Nov 2023 09:00:04 +0000 (17:00 +0800)]
clk: nuvoton: add read only feature for clk driver
Add a flag to set ahb/apb/fiu/spi clock divider as read-only
The spi clock setting is related to booting flash, it is setup by early
bootloader.
It just protects the clock source and can't modify it in uboot.
Igor Prusov [Thu, 9 Nov 2023 10:55:13 +0000 (13:55 +0300)]
clk: Add dump operation to clk_ops
This adds dump function to struct clk_ops which should replace
soc_clk_dump. It allows clock drivers to provide custom dump
implementation without overriding generic CCF dump function.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru>
[ Fixed parameter name in documentation ] Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20231109105516.24892-6-ivprusov@sberdevices.ru
Igor Prusov [Tue, 5 Dec 2023 23:23:33 +0000 (02:23 +0300)]
clk: Check that composite clock's div has set_rate()
It's possible for composite clocks to have a divider that does not
implement set_rate() operation. For example, sandbox_clk_composite()
registers composite clock with a divider that only has get_rate().
Currently clk_composite_set_rate() only checks thate rate_ops are
present, so for sandbox it will cause NULL dereference during
clk_set_rate().
This patch adds rate_ops->set_rate check tp clk_composite_set_rate().
Yang Xiwen [Fri, 10 Nov 2023 19:19:52 +0000 (03:19 +0800)]
clk: check parent_name in clk_register to avoid confusing log_error() output
For some gate clocks and fixed clocks without a parent, calling
clk_register will print an useless error message indicating that parent
is missing. Fix that by gaurding log_xxx() with an if-statement.
Tom Rini [Fri, 15 Dec 2023 14:41:44 +0000 (09:41 -0500)]
Merge patch series "bootm: Handle compressed arm64 images with bootm"
To quote the author:
This little series corrects a problem I noticed with arm64 images,
where the kernel is not recognised if compression is used:
U-Boot> tftp image.fit
Using ethernet@7d580000 device
TFTP from server 192.168.4.7; our IP address is 192.168.4.147
Filename 'image.fit'.
Load address: 0x1000000
Loading: ################################################## 23 MiB
20.5 MiB/s
done
Bytes transferred = 24118272 (1700400 hex)
U-Boot> bootm
## Loading kernel from FIT Image at 01000000 ...
Using 'conf-768' configuration
Trying 'kernel' kernel subimage
Description: Linux
Type: Kernel Image (no loading done)
Compression: gzip compressed
Data Start: 0x01000120
Data Size: 13662338 Bytes = 13 MiB
Verifying Hash Integrity ... OK
Bad Linux ARM64 Image magic!
With this series:
U-Boot> tftp 20000000 image.fit
Using ethernet@7d580000 device
TFTP from server 192.168.4.7; our IP address is 192.168.4.147
Filename 'image.fit'.
Load address: 0x20000000
Loading: ################################################## 23.5 MiB
20.8 MiB/s
done
Bytes transferred = 24642560 (1780400 hex)
U-Boot> bootm 0x20000000
## Loading kernel from FIT Image at 20000000 ...
Using 'conf-768' configuration
Trying 'kernel' kernel subimage
Description: Linux
Type: Kernel Image (no loading done)
Compression: zstd compressed
Data Start: 0x20000120
Data Size: 14333475 Bytes = 13.7 MiB
Verifying Hash Integrity ... OK
Using kernel load address 80000
## Loading fdt from FIT Image at 20000000 ...
Using 'conf-768' configuration
Trying 'fdt-768' fdt subimage
Description: Raspberry Pi 4 Model B
Type: Flat Device Tree
Compression: zstd compressed
Data Start: 0x215f820c
Data Size: 9137 Bytes = 8.9 KiB
Architecture: AArch64
Verifying Hash Integrity ... OK
Uncompressing Flat Device Tree to 3aff3010
Booting using the fdt blob at 0x3aff3010
Working FDT set to 3aff3010
Uncompressing Kernel Image (no loading done) to 80000
Moving Image from 0x80000 to 0x200000, end=2b00000
Using Device Tree in place at 000000003aff3010, end 000000003afff4c4
Working FDT set to 3aff3010
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd083]
The problem is that the arm64 magic is checked before the image is
decompressed. However this is only part of it. The kernel_noload image
type doesn't work with compression, since the kernel is not loaded. So
this series deals with that by using an lmb-allocated buffer for the
uncompressed kernel.
Another issue is that the arm64 handling is done too early, before the
image is loaded. This series moves it to after loading, so that
compression can be handled.
A patch is included to show the kernel load-address, so it is easy to
see what is going on.
One annoying feature of arm64 is that the image is often copied to
another address. It might be possible for U-Boot to figure that out
earlier and decompress it to the right place, but perhaps not.
With all of this it should be possible to boot a compressed kernel on
any of the 990 arm64 boards supported by Linux, although I have only
tested two.
Simon Glass [Sun, 19 Nov 2023 14:43:34 +0000 (07:43 -0700)]
bootm: Support kernel_noload with compression
It is not currently possible to execute the kernel in-place without
loading it. Use lmb to allocate memory for it.
Co-developed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Simon Glass <sjg@chromium.org> Suggested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Simon Glass [Sun, 19 Nov 2023 14:43:33 +0000 (07:43 -0700)]
bootm: Move arm64-image processing later
If the image is compressed, then the existing check fails, since the
header is wrong.
Move the check later in the boot process, after the kernel is
decompressed. This allows use of bootm with compressed kernels, while
still permitting an uncompressed kernel to be used.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Patrice Chotard [Fri, 17 Nov 2023 17:01:06 +0000 (18:01 +0100)]
board: st: common: Fix board_get_alt_info_mtd()
Since MTD devices are partioned, we got the following
error when command "dfu 0" is executed:
DFU alt info setting: done
ERROR: Too many arguments for nor0
ERROR: DFU entities configuration failed!
ERROR: (partition table does not match dfu_alt_info?)
Dario Binacchi [Mon, 11 Dec 2023 22:05:55 +0000 (23:05 +0100)]
board: stm32f469-disco: add support to display
Add support to Orise Tech OTM8009A display on stm32f469-disco board.
It was necessary to retrieve the framebuffer address from the device tree
because the address returned by the video-uclass driver pointed to a memory
area that was not usable.
Dario Binacchi [Mon, 11 Dec 2023 22:05:53 +0000 (23:05 +0100)]
ARM: dts: stm32: make the DSI clock usable by the clock driver
As described in [1], the "clocks" property contains "a phandle to the
clock device node, an index selecting between gated clocks (0) and other
clocks (1), and an index specifying the clock to use." The current version
of the clock driver, unlike the kernel, is currently able to properly
handle nodes with "clocks" properties with an index set to 0.
This patch is preparatory for future developments that require the use
of the DSI clock.
Dario Binacchi [Mon, 11 Dec 2023 22:05:52 +0000 (23:05 +0100)]
ARM: dts: stm32: make the LTDC clock usable by the clock driver
As described in [1], the "clocks" property contains "a phandle to the
clock device node, an index selecting between gated clocks (0) and other
clocks (1), and an index specifying the clock to use." The current version
of the clock driver, unlike the kernel, is currently able to properly
handle nodes with "clocks" properties with an index set to 0.
This patch is preparatory for future developments that require the use
of the LTDC clock.
Dario Binacchi [Sat, 11 Nov 2023 10:46:19 +0000 (11:46 +0100)]
clk: stm32f: fix setting of LCD clock
Set pllsaidivr only if the PLLSAIR output frequency is an exact multiple
of the pixel clock rate. Otherwise, we search through all combinations
of pllsaidivr * pllsair and use the one which gives the rate closest to
requested one.
Dario Binacchi [Sat, 11 Nov 2023 10:44:36 +0000 (11:44 +0100)]
ARM: dts: stm32f769-disco: rework ltdc node
With commit f479f5dbb7ac ("ARM: dts: stm32: add ltdc support on
stm32f746 MCU"), which adds the 'ltdc' node in stm32f746.dtsi, we can
simplify stm32f769-disco-uboot.dtsi and align stm32f769-disco.dtsi with
the kernel version.
Tom Rini [Fri, 15 Dec 2023 13:22:20 +0000 (08:22 -0500)]
Merge tag 'u-boot-imx-20231214' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
- Fix for i.MX8M Plus eDM SBC DDR timings with inline ECC
- Switch to FPWM mode on Data Modul i.MX8M Plus eDM SBC so that DRAM
EDAC detects more correctable errors
- Fix for imx8mp-venice board DDR initialization
Tim Harvey [Thu, 14 Dec 2023 16:22:26 +0000 (08:22 -0800)]
imx8mp-venice: fix DRAM bus configuration
The DRAM configuration for the 1GB and 4GB imx8mp venice boards had a
bus mapping issue (channel A and B swapped) which creates an invalid
deskewing configuration during training causing the DRAM to not be able
to run at its full bus speed.
Update the various config structures to resolve this.
Marek Vasut [Thu, 7 Dec 2023 17:50:32 +0000 (18:50 +0100)]
ARM: imx: Update DRAM timings with inline ECC on Data Modul i.MX8M Plus eDM SBC
Import DRAM timings generated by the DDR tool 3.31 which introduce assorted
tweaks to the DRAM controller settings. Furthermore, enable DBI to improve
noise resilience of the DRAM bus by reducing the number of bit changes on
the bus.
Reduce the DRAM rate to 3600 MTps to remove all remaining correctable errors
reported by EDAC . It is not entirely clear why the slightly faster setting
does produce sporadic correctable errors, while this one does not, but this
could be related to simpler PLL setting at 3600 MTps.
Enable inline ECC which is necessary to detect ECC errors and collect
statistics by the EDAC driver in Linux. This reduces the DRAM size by
64 MiB for each 512 MiB of DRAM, so for a 4 GiB device the available
DRAM size becomes 3.5 GiB .
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
Marek Vasut [Thu, 7 Dec 2023 17:50:31 +0000 (18:50 +0100)]
ARM: imx: Force DRAM regulators into FPWM mode on Data Modul i.MX8M Plus eDM SBC
In case the Buck5 and Buck6 regulators which supply DRAM Vdd1 and Vdd2/Vddq
respectively operate in automatic PWM/PFM mode, the DRAM EDAC detects more
correctable errors than if the regulators operate in forced PWM only mode.
Force DRAM regulators to forced PWM mode only to stop tempting the DRAM.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
Marek Vasut [Sat, 2 Dec 2023 01:58:28 +0000 (02:58 +0100)]
ARM: imx: Enable CAAM on DH i.MX8M Plus DHCOM
Enable CAAM in U-Boot to make crypto available early in the boot process.
This has a side-effect that in case an older kernel version contains a
broken CAAM initialization timeout code, initialization in bootloader
will help that old kernel version function correctly.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
Marek Vasut [Sat, 2 Dec 2023 01:55:06 +0000 (02:55 +0100)]
ARM: imx: Enable CAAM on Data Modul i.MX8M Mini/Plus eDM SBC
Enable CAAM in U-Boot to make crypto available early in the boot process.
This has a side-effect that in case an older kernel version contains a
broken CAAM initialization timeout code, initialization in bootloader
will help that old kernel version function correctly.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
Inhibit DTC warning in imx8mp-dhcom-pdk3-overlay-rev100.dts:
"
arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dtbo: Warning (reg_format): /fragment@0/__overlay__:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dtbo: Warning (avoid_default_addr_size): /fragment@0/__overlay__: Relying on default #address-cells value
arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dtbo: Warning (avoid_default_addr_size): /fragment@0/__overlay__: Relying on default #size-cells value
"
The DTO overwrites the 'reg' property of an ethernet PHY and is only
used on specific combination of old prototype SoM and old prototype
PDK3 carrier board, which had incorrectly placed pull resistor, which
made the PHY change its MDIO address in that specific combination and
which is already fixed on production hardware.
The DTO is implemented in this simple manner because if it contained a
full MDIO bus node reference to define #address-cells and #size-cells,
it would also require a full new copy of the PHY node, i.e.
ethernet-phy@5 { ... reg = <5>; ... }, to avoid DTC warnings about
mismatch between node unit and reg value. The node unit in SoM DT is
ethernet-phy@7 { ... }; .
This simpler approach avoids unnecessary duplication without adverse
side effects.
Reported-by: Fabio Estevam <festevam@denx.de> Reported-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de> Tested-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
This patch adds support for ESMT F50L1G41LB and F50D1G41LB.
It seems that ESMT likes to use random JEDEC ID from other vendors.
Their 1G chips uses 0xc8 from GigaDevice and 2G/4G chips uses 0x2c from
Micron. For this reason, the ESMT entry is named esmt_c8 with explicit
JEDEC ID in variable name.
projects / u-boot.git / log
