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3 years agomx7ulp: Update wdog disable sequence
Ye Li [Thu, 23 Sep 2021 14:01:15 +0000 (17:01 +0300)]
mx7ulp: Update wdog disable sequence

Update the mx7ulp wdog disable sequence to avoid potential reset
issue in unlock or refresh sequence. Both sequence need two words
write to wdog CNT register in 16 bus clocks window, if miss the
window, the write will cause violation in wdog and reset the chip.

Current u-boot code is using writel() function which has a DMB
barrier to order the memory access. The DMB between two words write
may introduce some delay in certain circumstance, causing the wdog
reset due to 16 bus clock window requirement.

Also, WDOG1 might have been enabled already depending on FUSE hence
we need to be as close as possible to its reconfiguration timing
requirement of 128 bus clock limit.

This patch replaces writel() function by __raw_writel() to avoid such
issue, and improve to check if watchdog is already disabled or
unlocked.

Signed-off-by: Ye Li <ye.li@nxp.com>
Co-developed-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Co-developed-by: Ricardo Salveti <ricardo@foundries.io>
Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
3 years agortc: rv8803: add epson,rx8803 and epson,rx8900 compatible
Heiko Thiery [Thu, 23 Sep 2021 09:14:32 +0000 (11:14 +0200)]
rtc: rv8803: add epson,rx8803 and epson,rx8900 compatible

The RX8803 and RX8900 register layouts are compatible with the one of
the RV8803. So add these to the compatibles.

The same compatible strings are used and approved in linux kernel.

Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Michael Walle <michael@walle.cc>
3 years agoARM: dts: imx6-apalis: enable watchdog
Ricardo Salveti [Tue, 21 Sep 2021 11:48:26 +0000 (14:48 +0300)]
ARM: dts: imx6-apalis: enable watchdog

Add u-boot.dtsi specific to imx6-apalis with a watchdog enabled.

If OP-TEE is loaded by SPL, it may use a watchdog to handle fails of
u-boot running. Enable the watchdog in SPL to use it by OP-TEE.

Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
3 years agoARM: dts: imx8mm-verdin: Set PHY mode to RGMII-ID
Marek Vasut [Sat, 11 Sep 2021 22:43:18 +0000 (00:43 +0200)]
ARM: dts: imx8mm-verdin: Set PHY mode to RGMII-ID

Since c6df0e2ffdc ("net: phy: micrel: add support for DLL setup on ksz9131")
the Micrel PHY driver correctly configures the delay register. The Verdin PHY
is RGMII-ID, so reflect that in DT, otherwise the ethernet no longer works.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Max Krummenacher <max.krummenacher@toradex.com>
Cc: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
3 years agoimx8qm_mek: Increase CONFIG_SYS_BOOTM_LEN to 64MB
Oleksandr Suvorov [Sun, 29 Aug 2021 19:39:13 +0000 (22:39 +0300)]
imx8qm_mek: Increase CONFIG_SYS_BOOTM_LEN to 64MB

The BSP platform LmP supports the board NXP iMX8QM MEK. The
kernel size in LmP exceeds 32Mb. Increase the maximum size
of an uncompressed kernel to fix the following error:
    Uncompressing Kernel Image
    Error: inflate() returned -5
    Image too large: increase CONFIG_SYS_BOOTM_LEN
    Must RESET board to recover

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
3 years agoimx8mq_evk: Increase CONFIG_SYS_BOOTM_LEN to 64MB
Oleksandr Suvorov [Sun, 29 Aug 2021 19:39:12 +0000 (22:39 +0300)]
imx8mq_evk: Increase CONFIG_SYS_BOOTM_LEN to 64MB

The BSP platform LmP supports the board NXP iMX8M Plus EVK. The
kernel size in LmP exceeds 32Mb. Increase the maximum size
of an uncompressed kernel to fix the following error:
    Uncompressing Kernel Image
    Error: inflate() returned -5
    Image too large: increase CONFIG_SYS_BOOTM_LEN
    Must RESET board to recover

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
3 years agoimx8mm_evk: Increase CONFIG_SYS_BOOTM_LEN to 64MB
Oleksandr Suvorov [Sun, 29 Aug 2021 19:39:11 +0000 (22:39 +0300)]
imx8mm_evk: Increase CONFIG_SYS_BOOTM_LEN to 64MB

The BSP platform LmP supports the board NXP iMX8M Mini EVK. The
kernel size in LmP exceeds 32Mb. Increase the maximum size
of an uncompressed kernel to fix the following error:
    Uncompressing Kernel Image
    Error: inflate() returned -5
    Image too large: increase CONFIG_SYS_BOOTM_LEN
    Must RESET board to recover

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
3 years agoKconfig: Don't use RSA_FREESCALE_EXP on MX7ULP
Ricardo Salveti [Sat, 28 Aug 2021 07:41:22 +0000 (10:41 +0300)]
Kconfig: Don't use RSA_FREESCALE_EXP on MX7ULP

The CAAM on IMX7ULP doesn't support public key hardware acceleration
(PKHA), as in other NXP parts. Disable RSA_FREESCALE_EXP for IMX7ULP
too.

Fixed: f4e9ff7135 ("Kconfig: Don't use RSA_FREESCALE_EXP on IMX")
Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
3 years agoarm: dts: imx8mp: Generate single bootable binary
Teresa Remmet [Thu, 26 Aug 2021 08:54:09 +0000 (10:54 +0200)]
arm: dts: imx8mp: Generate single bootable binary

binman conversion made flashing flash.bin
and u-boot.itb necessary. Update binman config
to create a single flash.bin image again.

This updates imx8mp_evk and phyCORE-i.MX8MP as they share the
same binman config.

Updated also imx8mp_evk documentation.

Tested on phyCORE-i.MX8MP.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
3 years agoarm: imx8m: imx8mm-cl-iot-gate: Add support for detect memory size
Ying-Chun Liu (PaulLiu) [Tue, 24 Aug 2021 09:44:19 +0000 (17:44 +0800)]
arm: imx8m: imx8mm-cl-iot-gate: Add support for detect memory size

When purchasing imx8mm-cl-iot-gate it is able to customize the
memory size. It could be 1GB, 2GB and 4GB. We implement
board_phys_sdram_size() to detect the memory size for usage.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Frieder Schrempf <frieder.schrempf@kontron.de>
Cc: uboot-imx <uboot-imx@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
3 years agotree: imx: remove old fit generator script
Andrey Zhizhikin [Tue, 24 Aug 2021 07:55:14 +0000 (09:55 +0200)]
tree: imx: remove old fit generator script

Since derivatives are moving to binman from usage of the FIT generator
script, and considering the warning introduced in f4a43d2925
("Makefile: Warn against using CONFIG_SPL_FIT_GENERATOR"), usage of FIT
generator is discouraged.

Current FIT generator also generates broken output, since commit
3f04db891a ("image: Check for unit addresses in FITs") prohibits using
'@' for unit addresses but the generator script still emits the old
sematics.

Remove the generator script and corresponding call in Makefile, all
derivatives should be migrated to binman in order to provide binary
images.

Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
3 years agoimx8mm-cl-iot-gate: Split the defconfigs
Fabio Estevam [Tue, 24 Aug 2021 00:11:09 +0000 (21:11 -0300)]
imx8mm-cl-iot-gate: Split the defconfigs

Currently imx8mm-cl-iot-gate_defconfig fails to produce a working boot
binary due to the lack of fip.bin:

"  BINMAN  all
Image 'main-section' is missing external blobs and is non-functional: blob-ext

Some images are invalid"

To make the build process more consistent with the other i.MX8M targets,
split the defconfig in two:

- imx8mm-cl-iot-gate_defconfig: standard defconfig that only
requires ATF / DDR firmware.

- imx8mm-cl-iot-gate-optee_defconfig: "more advanced" defconfig that
requires ATF / Optee / mbedtls / DDR firmware.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
3 years agomx7ulp: Allow to enable CONFIG_IMX_HAB
Ricardo Salveti [Mon, 23 Aug 2021 11:55:12 +0000 (14:55 +0300)]
mx7ulp: Allow to enable CONFIG_IMX_HAB

Secure boot support on mx7ulp was added in the
commit 27117b2024b6 ("mx7ulp: Add HAB boot support").

Allow selecting CONFIG_IMX_HAB for ARCH_IMX7ULP.

Fixes: 27117b2024b6 ("mx7ulp: Add HAB boot support")
Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
3 years agoimx8m: Restrict usable memory based on rom_pointer[0]
Ying-Chun Liu (PaulLiu) [Mon, 23 Aug 2021 02:43:06 +0000 (10:43 +0800)]
imx8m: Restrict usable memory based on rom_pointer[0]

When TEE is loaded, we need to restrict the memory usage based
on rom_pointer[0]

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Frieder Schrempf <frieder.schrempf@kontron.de>
Cc: uboot-imx <uboot-imx@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
3 years agoarm: dts: imx8mm-venice*: remove thermal zone overrides
Tim Harvey [Wed, 18 Aug 2021 22:24:31 +0000 (15:24 -0700)]
arm: dts: imx8mm-venice*: remove thermal zone overrides

Remove the unnecessary thermal zone overrides.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
3 years agoboard: gateworks: venice: update thermal temp thresholds per cpu grade
Tim Harvey [Wed, 18 Aug 2021 22:24:30 +0000 (15:24 -0700)]
board: gateworks: venice: update thermal temp thresholds per cpu grade

Update the passive/critical thermal zone dt config per CPU temperature
grade.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
3 years agoarm: dts: imx8mm-venice-gw700x: fix mp5416 pmic config
Tim Harvey [Wed, 18 Aug 2021 22:24:29 +0000 (15:24 -0700)]
arm: dts: imx8mm-venice-gw700x: fix mp5416 pmic config

Fix various MP5416 PMIC configurations:
 - Update regulator names per dt-bindings
 - ensure values fit among valid register values
 - add required regulator-max-microamp property
 - add regulator-always-on prop

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
3 years agoboard: gateworks: venice: do not overwrite serial#
Tim Harvey [Wed, 18 Aug 2021 22:24:28 +0000 (15:24 -0700)]
board: gateworks: venice: do not overwrite serial#

Do not overwrite existing serial# env to avoid:
 ## Error: Can't overwrite "serial#"
 ## Error inserting "serial#" variable, errno=1

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
3 years agoboard: gateworks: venice: display hwmon details by default
Tim Harvey [Wed, 18 Aug 2021 22:24:27 +0000 (15:24 -0700)]
board: gateworks: venice: display hwmon details by default

Display hwmon values by default when using the 'gsc' command.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
3 years agoimx53: usbarmory: Add card detect configuration
Andrej Rosano [Tue, 17 Aug 2021 09:34:02 +0000 (11:34 +0200)]
imx53: usbarmory: Add card detect configuration

After the enforcement of DM_MMC the microSD card is not detected. Fix by
correctly configuring the card detect in the devicetree.

Signed-off-by: Andrej Rosano <andrej.rosano@f-secure.com>
3 years agomtd: nand: mxs_nand_spl: Add nand_spl_adjust_offset
Ye Li [Tue, 17 Aug 2021 09:24:47 +0000 (17:24 +0800)]
mtd: nand: mxs_nand_spl: Add nand_spl_adjust_offset

Since the mxs_nand_spl has implemented adjust read offset in
nand_spl_load_image, so we don't need to check the bad block in
nand_spl_adjust_offset. Directly return the offset to continue
read by nand_spl_load_image.

Signed-off-by: Ye Li <ye.li@nxp.com>
3 years agoarm: imx8m: Fix pad DSE issue for i.MX8MM/MN/MP
Ye Li [Tue, 17 Aug 2021 09:10:35 +0000 (17:10 +0800)]
arm: imx8m: Fix pad DSE issue for i.MX8MM/MN/MP

According to 8MM/MN/MP reference manual, their pad registers only have
4 valid DSE values. And DSE2 and DSE4 are different with current
definitions in iomux-v3.h. Fix the issue to align with manual.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
3 years agommc: fsl_esdhc_imx: Fix clock disable issue
Ye Li [Tue, 17 Aug 2021 09:09:20 +0000 (17:09 +0800)]
mmc: fsl_esdhc_imx: Fix clock disable issue

The SD clock disable is wrapped by MMC_SUPPORTS_TUNING. So it
only works when UHS is enabled. However, in SD initialization the
power cycle does not depends on UHS. But the power cycle needs
disable the SD clock before power down.
So this causes a problem when UHS is not enabled. Some cards can't
become ready (ACMD14 timeout) due to the clock is enabled during
power cycle.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
3 years agoimx: spl: fix imx8m secure boot
Heiko Schocher [Tue, 17 Aug 2021 06:17:18 +0000 (08:17 +0200)]
imx: spl: fix imx8m secure boot

cherry-picked from NXP code:
719d665a87c6: ("MLK-20467 imx8m: Fix issue for booting signed image through uuu")

which fixes secure boot on imx8m based boards. Problem was
that FIT header and so IVT header too, was loaded to
memallocated address. So the ivt header address coded
in IVT itself does not fit with the real position.

Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Tim Harvey <tharvey@gateworks.com>
3 years agoimx: spl: implement spl_load_simple_fit_fix_load
Heiko Schocher [Fri, 6 Aug 2021 04:44:27 +0000 (06:44 +0200)]
imx: spl: implement spl_load_simple_fit_fix_load

read the address where the IVT header must sit
from IVT image header, loaded from SPL into
an malloced buffer and copy the IVT header
to this address

May make this dependend on SoC ?

Signed-off-by: Heiko Schocher <hs@denx.de>
3 years agospl_fit. add hook to make fixes after fit header is loaded
Heiko Schocher [Fri, 6 Aug 2021 04:44:26 +0000 (06:44 +0200)]
spl_fit. add hook to make fixes after fit header is loaded

add hook function spl_load_simple_fit_fix_load()
which is called after fit image header is loaded.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agomtd: nand: Fix typo in MXC Kconfig symbol description
Haolin Li [Sun, 18 Jul 2021 02:13:39 +0000 (10:13 +0800)]
mtd: nand: Fix typo in MXC Kconfig symbol description

Trivial typo fix.

Signed-off-by: Haolin Li <li.haolin@qq.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
3 years agoMerge branch '2021-10-06-assorted-improvements'
Tom Rini [Wed, 6 Oct 2021 16:26:33 +0000 (12:26 -0400)]
Merge branch '2021-10-06-assorted-improvements'

- Use better values for ACPI OEM_VERSION
- Assorted NAND related Kconifg migrations and another dependency fix

3 years agoConvert CONFIG_NAND_OMAP_ECCSCHEME to Kconfig
Tom Rini [Wed, 22 Sep 2021 18:50:39 +0000 (14:50 -0400)]
Convert CONFIG_NAND_OMAP_ECCSCHEME to Kconfig

The values of CONFIG_NAND_OMAP_ECCSCHEME map to the enum in
include/linux/mtd/omap_gpmc.h for valid ECC schemes.  Make which one we
will use be a choice statement, enumerating the ones which we have
implemented.

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoConvert CONFIG_SYS_NAND_U_BOOT_LOCATIONS et al to Kconfig
Tom Rini [Wed, 22 Sep 2021 18:50:38 +0000 (14:50 -0400)]
Convert CONFIG_SYS_NAND_U_BOOT_LOCATIONS et al to Kconfig

This converts the following to Kconfig:
   CONFIG_SYS_NAND_U_BOOT_LOCATIONS
   CONFIG_SYS_NAND_U_BOOT_OFFS

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoConvert CONFIG_NAND_FSL_ELBC et al to Kconfig
Tom Rini [Wed, 22 Sep 2021 18:50:37 +0000 (14:50 -0400)]
Convert CONFIG_NAND_FSL_ELBC et al to Kconfig

This converts the following to Kconfig:
   CONFIG_NAND_FSL_ELBC
   CONFIG_NAND_FSL_IFC

Note that a number of PowerPC platforms had previously enabled
CONFIG_NAND_FSL_ELBC without CONFIG_MTD_RAW_NAND, and now they no longer
enable the option, reducing the size of a few functions.

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoConvert CONFIG_SYS_NAND_MAX_CHIPS to Kconfig
Tom Rini [Wed, 22 Sep 2021 18:50:36 +0000 (14:50 -0400)]
Convert CONFIG_SYS_NAND_MAX_CHIPS to Kconfig

This converts the following to Kconfig:
   CONFIG_SYS_NAND_MAX_CHIPS

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agonand.h: Cleanup linux/mtd/rawnand.h usage
Tom Rini [Wed, 22 Sep 2021 18:50:35 +0000 (14:50 -0400)]
nand.h: Cleanup linux/mtd/rawnand.h usage

We only include <linux/mtd/rawnand.h> in <nand.h> for the forward
declaration of struct nand_chip, so do that directly.  Then, include
<linux/mtd/rawnand.h> where required directly.

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoConvert CONFIG_SYS_NAND_ONFI_DETECTION to Kconfig
Tom Rini [Wed, 22 Sep 2021 18:50:34 +0000 (14:50 -0400)]
Convert CONFIG_SYS_NAND_ONFI_DETECTION to Kconfig

This converts the following to Kconfig:
   CONFIG_SYS_NAND_ONFI_DETECTION

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoConvert CONFIG_SYS_NAND_5_ADDR_CYCLE to Kconfig
Tom Rini [Wed, 22 Sep 2021 18:50:33 +0000 (14:50 -0400)]
Convert CONFIG_SYS_NAND_5_ADDR_CYCLE to Kconfig

This converts the following to Kconfig:
   CONFIG_SYS_NAND_5_ADDR_CYCLE

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoConvert CONFIG_SYS_NAND_BAD_BLOCK_POS to Kconfig
Tom Rini [Wed, 22 Sep 2021 18:50:32 +0000 (14:50 -0400)]
Convert CONFIG_SYS_NAND_BAD_BLOCK_POS to Kconfig

This converts the following to Kconfig:
   CONFIG_SYS_NAND_BAD_BLOCK_POS

In order to do this, introduce a choice for HAS_LARGE/SMALL_BADBLOCK_POS
as those are the only valid values.  Use LARGE as the default as no
in-tree boards use SMALL, but it is possible.

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agonand_spl_simple: Drop CONFIG_SYS_NAND_4_ADDR_CYCLE support
Tom Rini [Wed, 22 Sep 2021 18:50:31 +0000 (14:50 -0400)]
nand_spl_simple: Drop CONFIG_SYS_NAND_4_ADDR_CYCLE support

This code is unused, drop it.

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoConvert CONFIG_SYS_NAND_PAGE_COUNT to Kconfig
Tom Rini [Wed, 22 Sep 2021 18:50:30 +0000 (14:50 -0400)]
Convert CONFIG_SYS_NAND_PAGE_COUNT to Kconfig

This converts the following to Kconfig:
   CONFIG_SYS_NAND_PAGE_COUNT

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoConvert CONFIG_SPL_NAND_LOAD et al to Kconfig
Tom Rini [Wed, 22 Sep 2021 18:50:29 +0000 (14:50 -0400)]
Convert CONFIG_SPL_NAND_LOAD et al to Kconfig

This converts the following to Kconfig:
   CONFIG_SPL_NAND_LOAD
   CONFIG_SYS_NAND_BLOCK_SIZE
   CONFIG_SYS_NAND_PAGE_SIZE
   CONFIG_SYS_NAND_OOBSIZE

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoConvert CONFIG_NAND_LPC32XX_MLC to Kconfig
Tom Rini [Wed, 22 Sep 2021 18:50:28 +0000 (14:50 -0400)]
Convert CONFIG_NAND_LPC32XX_MLC to Kconfig

This converts the following to Kconfig:
   CONFIG_NAND_LPC32XX_MLC

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agom53menlo: Switch to deriving CONFIG_SYS_NAND_PAGE_COUNT
Tom Rini [Wed, 22 Sep 2021 18:50:27 +0000 (14:50 -0400)]
m53menlo: Switch to deriving CONFIG_SYS_NAND_PAGE_COUNT

Typically platforms will define CONFIG_SYS_NAND_PAGE_COUNT based on
CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE.  Switch to this
in preparation for migrating CONFIG_SYS_NAND namespace to Kconfig.

Cc: Marek Vasut <marex@denx.de>
Cc: Olaf Mandel <o.mandel@menlosystems.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agork3308: Remove unused NAND defines
Tom Rini [Wed, 22 Sep 2021 18:50:26 +0000 (14:50 -0400)]
rk3308: Remove unused NAND defines

These platforms do not currently enable NAND, remove these references.

Cc: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agolib: rsa: fix dependency for SPL_RSA_VERIFY
Oleksandr Suvorov [Thu, 16 Sep 2021 12:03:36 +0000 (15:03 +0300)]
lib: rsa: fix dependency for SPL_RSA_VERIFY

SPL_RSA_VERIFY requires SPL_RSA to be enabled. Add correct
dependency.

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
3 years agoacpi: Use U-Boot version for OEM_REVISION
Pali Rohár [Sat, 10 Jul 2021 11:10:01 +0000 (13:10 +0200)]
acpi: Use U-Boot version for OEM_REVISION

OEM_REVISION is 32-bit unsigned number. It should be increased only when
changing software version. Therefore it should not depend on build time.

Change calculation to use U-Boot version numbers and set this revision
to date number.

Prior this change OEM_REVISION was calculated from build date and stored in
the same format.

After this change macro U_BOOT_BUILD_DATE is not used in other files so
remove it from global autogenerated files and also from Makefile.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoMerge branch '2021-10-05-general-updates'
Tom Rini [Tue, 5 Oct 2021 21:16:23 +0000 (17:16 -0400)]
Merge branch '2021-10-05-general-updates'

- Assorted OPTEE cleanups
- pinctrl, gpio improvements, assorted livetree migrations
- Assorted pytest improvements

3 years agoreboot-mode: migrate uclass to livetree
Patrick Delaunay [Mon, 20 Sep 2021 16:27:20 +0000 (18:27 +0200)]
reboot-mode: migrate uclass to livetree

Use dev_ function to support a live tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agodemo: migrate uclass to livetree
Patrick Delaunay [Mon, 20 Sep 2021 15:58:33 +0000 (17:58 +0200)]
demo: migrate uclass to livetree

Use dev_ function to read the sides and colour to support a live tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoremoteproc: migrate uclass to livetree
Patrick Delaunay [Mon, 20 Sep 2021 15:56:06 +0000 (17:56 +0200)]
remoteproc: migrate uclass to livetree

Use dev_ function to read the name and boolean to support a live tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agodoc: test: Explain how to run pytests in parallel
Simon Glass [Sun, 19 Sep 2021 21:14:51 +0000 (15:14 -0600)]
doc: test: Explain how to run pytests in parallel

Add documentation for this so people can try it out. At present it does
not fully work.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agotest: Allow tpm2 tests to run in parallel
Simon Glass [Sun, 19 Sep 2021 21:14:50 +0000 (15:14 -0600)]
test: Allow tpm2 tests to run in parallel

These tests currently run in a particular sequence, with some of them
depending on the actions of earlier tests.

Add a check for sandbox and reset to a known state at the start of each
test, so that all tests can run in parallel.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agotest: Allow hush tests to run in parallel
Simon Glass [Sun, 19 Sep 2021 21:14:49 +0000 (15:14 -0600)]
test: Allow hush tests to run in parallel

The -z tests don't really need to be part of the main set. Separate them
out so we can drop the test setup/cleans functions and thus run all tests
in parallel.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agotest: Allow vboot tests to run in parallel
Simon Glass [Sun, 19 Sep 2021 21:14:48 +0000 (15:14 -0600)]
test: Allow vboot tests to run in parallel

Update the tests to use separate working directories, so we can run them
in parallel. It also makes it possible to see the individual output files
after the tests have completed.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agotest/py: Check hashes produced by mkimage against known values
Alexandru Gagniuc [Wed, 15 Sep 2021 19:33:01 +0000 (14:33 -0500)]
test/py: Check hashes produced by mkimage against known values

Target code and mkimage share the same hashing infrastructure. If one
is wrong, it's very likely that both are wrong in the same way. Thus
testing won't catch hash regressions. This already happened in
commit 92055e138f28 ("image: Drop if/elseif hash selection in
calculate_hash()"). None of the tests caught that CRC32 was broken.

Instead of testing hash_calculate() against itself, create a FIT with
containing a kernel with pre-calculated hashes. Then check the hashes
produced against the known good hashes.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agogpio: Factor out DT flag translation
Samuel Holland [Sat, 11 Sep 2021 22:05:53 +0000 (17:05 -0500)]
gpio: Factor out DT flag translation

The generic GPIO flags binding is shared across many drivers, some of
which need their own xlate function. Factor out the flag translation
code from gpio_xlate_offs_flags so it does not need to be duplicated.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agogpio: Verify validity of pin offsets from device trees
Samuel Holland [Sat, 11 Sep 2021 22:05:52 +0000 (17:05 -0500)]
gpio: Verify validity of pin offsets from device trees

Translation of an OF GPIO specifier should fail if the pin offset is
larger than the number of pins in the GPIO bank.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agogpio: Verify validity of pin offsets when looking up names
Samuel Holland [Sat, 11 Sep 2021 22:05:51 +0000 (17:05 -0500)]
gpio: Verify validity of pin offsets when looking up names

Translation of a pin name to a device+offset should fail if the offset
is larger than the number of pins in the GPIO bank.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoarm: imx: mx7: Move CONFIG_OPTEE_TZDRAM_SIZE from lib/optee
Alexandru Gagniuc [Tue, 7 Sep 2021 17:07:09 +0000 (12:07 -0500)]
arm: imx: mx7: Move CONFIG_OPTEE_TZDRAM_SIZE from lib/optee

This config is only used by three boards with this SOC. Most other
platforms derive this information from devicetree, and are unlikely
to ever need this config.

Moreover, it is confusing when Kconfig asks for this value under
"Support OPTEE images", but does not do anything with the value.
Move it to imx7 for those boards who still make use of it.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
3 years agolib: optee: Remove CONFIG_OPTEE_LOAD_ADDR
Alexandru Gagniuc [Tue, 7 Sep 2021 17:07:08 +0000 (12:07 -0500)]
lib: optee: Remove CONFIG_OPTEE_LOAD_ADDR

This value is not used by u-boot, and it should not. The load address
of an OPTEE image is defined by said image. Either a uImage or a FIT
will have a defined load address and entry point. Those values are the
correct ones, not CONFIG_OPTEE_LOAD_ADDR.

Commit f25006b96e9f ("optee: Add CONFIG_OPTEE_LOAD_ADDR") justifies
this config by requiring its presence in u-boot's .config for other
images as part of a larger build, claiming it is "the best way".

This argument is not persuasive. U-boot's configuration is driven by
platform requirements, not the other way around. It seems more likely
that the argument is conflating tooling issues with Kconfig. Yocto and
buildroot have excellent mechanisms for defining values across the
board (pun intended). u-boot's Kconfig is the wrong place to do it.

Furthermore, it is not "best" for u-boot because it hardcodes a value
which is then not used. In fact the load address that u-boot uses is
the one derived from the OPTEE image.

Confused yet? I sure was. To prevent future confusion, remove
CONFIG_OPTEE_LOAD_ADDR.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
3 years agolib: optee: Remove CONFIG_OPTEE_TZDRAM_BASE
Alexandru Gagniuc [Tue, 7 Sep 2021 17:07:07 +0000 (12:07 -0500)]
lib: optee: Remove CONFIG_OPTEE_TZDRAM_BASE

It is no longer used in u-boot. Information about the TZDRAM location
is usually available in the devicetree as "/reserved-memory/" nodes.
Because this isn't used, remove it.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
3 years agolib: optee: Avoid CONFIG_TZDRAM_* in optee_verify_bootm_image()
Alexandru Gagniuc [Tue, 7 Sep 2021 17:07:06 +0000 (12:07 -0500)]
lib: optee: Avoid CONFIG_TZDRAM_* in optee_verify_bootm_image()

The configs TZDRAM_BASE and TZDRAM_SIZE are expected to describe the
memory allocated to the OPTEE region. according to according to commit
c5a6e8bd00cc ("optee: Add optee_verify_bootm_image()"). The TZDRAM is
with some limitations, described by "/reserved-memory" nodes in the
devicetree.

Consequently TZDRAM_BASE and TZDRAM_SIZE can point to imaginary
regions which have nothing to do with actual DRAM. They are not used
to configure the hardware or set up the Trust Zone Controller (TZC)
for OP-TEE -- the devicetree values are used instead.

When a valid OP-TEE image does not fall within the region described by
these configs, u-boot will refuse to load it. In fact, it mostly
serves to cause "bootm" to reject perfectly good OP-TEE images.

Ironically, someone has to correctly configure the devicetree for
TZDRAM, then go back and enter the same information in Kconfig for
"bootm". To remedy this, do not use TZDRAM_BASE and TZDRAM_SIZE in the
verification of OPTEE images.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
3 years agotee: add a stub for tee_find_device
Patrick Delaunay [Thu, 2 Sep 2021 09:56:17 +0000 (11:56 +0200)]
tee: add a stub for tee_find_device

Add stub for tee_find_device function when CONFIG_TEE is not activated
to simplify the caller code.

This patch allows to remove the CONFIG_IS_ENABLED(OPTEE) tests
for stm32 platform.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@inaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
3 years agolib: optee: remove the duplicate CONFIG_OPTEE
Patrick Delaunay [Thu, 2 Sep 2021 09:56:16 +0000 (11:56 +0200)]
lib: optee: remove the duplicate CONFIG_OPTEE

The configuration CONFIG_OPTEE is defined 2 times:
1- in lib/optee/Kconfig for support of OPTEE images loaded by bootm command
2- in drivers/tee/optee/Kconfig for support of OP-TEE driver.

It is abnormal to have the same CONFIG define for 2 purpose;
and it is difficult to managed correctly their dependencies.

Moreover CONFIG_SPL_OPTEE is defined in common/spl/Kconfig
to manage OPTEE image load in SPL.

This definition causes an issue with the macro CONFIG_IS_ENABLED(OPTEE)
to test the availability of the OP-TEE driver.

This patch cleans the configuration dependency with:
- CONFIG_OPTEE_IMAGE (renamed) => support of OP-TEE image in U-Boot
- CONFIG_SPL_OPTEE_IMAGE (renamed) => support of OP-TEE image in SPL
- CONFIG_OPTEE (same) => support of OP-TEE driver in U-Boot
- CONFIG_OPTEE_LIB (new) => support of OP-TEE library

After this patch, the macro have the correct behavior:
- CONFIG_IS_ENABLED(OPTEE_IMAGE) => Load of OP-TEE image is supported
- CONFIG_IS_ENABLED(OPTEE) => OP-TEE driver is supported

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
3 years agopinctrl: single: Add request() api
Bharat Gooty [Tue, 24 Aug 2021 10:16:32 +0000 (15:46 +0530)]
pinctrl: single: Add request() api

Add pinctrl_ops->request api to configure pctrl
pad register in gpio mode.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
Acked-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agopinctrl: single: Parse gpio details from dt
Bharat Gooty [Tue, 24 Aug 2021 10:16:31 +0000 (15:46 +0530)]
pinctrl: single: Parse gpio details from dt

Parse different gpio properties from dt as part of probe
function. This detail is required to enable pinctrl pad
later when gpio lines are requested.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
Acked-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
3 years agoMerge branch 'next'
Tom Rini [Mon, 4 Oct 2021 15:27:55 +0000 (11:27 -0400)]
Merge branch 'next'

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoPrepare v2021.10
Tom Rini [Mon, 4 Oct 2021 15:09:26 +0000 (11:09 -0400)]
Prepare v2021.10

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agomtd: cqspi: Fix division by zero
Marek Vasut [Tue, 14 Sep 2021 03:21:48 +0000 (05:21 +0200)]
mtd: cqspi: Fix division by zero

Both dummy.nbytes and dummy.buswidth may be zero. By not checking
the later, it is possible to trigger division by zero and a crash.
This does happen with tiny SPI NOR framework in SPL. Fix this by
adding the check and returning zero dummy bytes in such a case.

Fixes: 38b0852b0ea ("spi: cadence-qspi: Add support for octal DTR flashes")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Pratyush Yadav <p.yadav@ti.com>
[trini: Drop Pratyush's RB as his requested changes weren't made as
        Marek disagreed]

3 years agoMerge branch '2021-10-03-platform-updates' into next
Tom Rini [Sun, 3 Oct 2021 23:31:04 +0000 (19:31 -0400)]
Merge branch '2021-10-03-platform-updates' into next

- TI K3 updates, add IOT2050 platform
- rtc rx8025 updates, PCI fixes

3 years agoiot2050: Enable watchdog support, but do not auto-start it
Jan Kiszka [Sat, 18 Sep 2021 06:17:56 +0000 (08:17 +0200)]
iot2050: Enable watchdog support, but do not auto-start it

This allows to use the watchdog in custom scripts but does not enforce
that the OS has to support it as well.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
3 years agowatchdog: rti_wdt: Add support for loading firmware
Jan Kiszka [Sat, 18 Sep 2021 06:17:55 +0000 (08:17 +0200)]
watchdog: rti_wdt: Add support for loading firmware

To avoid the need of extra boot scripting on AM65x for loading a
watchdog firmware, add the required rproc init and loading logic for the
first R5F core to the watchdog start handler. In case the R5F cluster is
in lock-step mode, also initialize the second core. The firmware itself
is embedded into U-Boot binary to ease access to it and ensure it is
properly hashed in case of secure boot.

One possible firmware source is https://github.com/siemens/k3-rti-wdt.

The board is responsible for providing the firmware as additional
loadable via the U-Boot fit image. The driver will pick up its location
from /fit-images/k3-rti-wdt-firmware then.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
3 years agoboard: siemens: Add support for SIMATIC IOT2050 devices
Jan Kiszka [Sat, 18 Sep 2021 06:17:53 +0000 (08:17 +0200)]
board: siemens: Add support for SIMATIC IOT2050 devices

This adds support for the IOT2050 Basic and Advanced devices. The Basic
used the dual-core AM6528 GP processor, the Advanced one the AM6548 HS
quad-core version.

Both variants are booted via a Siemens-provided FSBL that runs on the R5
cores. Consequently, U-Boot support is targeting the A53 cores. U-Boot
SPL, ATF and TEE have to reside in SPI flash.

Full integration into a bootable image can be found on
https://github.com/siemens/meta-iot2050

Based on original board support by Le Jin, Gao Nian and Chao Zeng.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
3 years agoarm: dts: Add IOT2050 device tree files
Jan Kiszka [Sat, 18 Sep 2021 06:17:52 +0000 (08:17 +0200)]
arm: dts: Add IOT2050 device tree files

Prepares for the addition of the IOT2050 board which is based on the TI
AM65x. The board comes in four variants, Basic and Advanced, each as
product generation 1 (SR1.0) and 2 (SR2.x), so there are separate dts
files needed. Furthermore, the SPL has its own device tree.

Based on original board support by Le Jin, Gao Nian and Chao Zeng.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
3 years agopci: pcie_layerscape_fixup_common: lx2_board_fix_fdt can be static
Vladimir Oltean [Fri, 17 Sep 2021 12:11:30 +0000 (15:11 +0300)]
pci: pcie_layerscape_fixup_common: lx2_board_fix_fdt can be static

To avoid W=1 build warnings, declare this function as static, since it
is not used outside of this translation module.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agopci: pcie_layerscape_fixup_common: include fdt_support.h for ft_pci_setup
Vladimir Oltean [Fri, 17 Sep 2021 12:11:29 +0000 (15:11 +0300)]
pci: pcie_layerscape_fixup_common: include fdt_support.h for ft_pci_setup

The function prototype for ft_pci_setup is inside fdt_support.h, we need
to include that header.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agopci: layerscape: ls_pcie_conf_address can be static
Vladimir Oltean [Fri, 17 Sep 2021 12:11:28 +0000 (15:11 +0300)]
pci: layerscape: ls_pcie_conf_address can be static

To avoid W=1 build warnings, declare this function as static, since it
is not used outside of this translation module.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agopci: _dm_pci_phys_to_bus can be static
Vladimir Oltean [Fri, 17 Sep 2021 12:11:27 +0000 (15:11 +0300)]
pci: _dm_pci_phys_to_bus can be static

To avoid W=1 build warnings, declare this function as static, since it
is not used outside of this translation module.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agopci: pci_read_config can be static
Vladimir Oltean [Fri, 17 Sep 2021 12:11:26 +0000 (15:11 +0300)]
pci: pci_read_config can be static

To avoid W=1 build warnings, declare this function as static, since it
is not used outside of this translation module.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agopci: pci_write_config can be static
Vladimir Oltean [Fri, 17 Sep 2021 12:11:25 +0000 (15:11 +0300)]
pci: pci_write_config can be static

To avoid W=1 build warnings, declare this function as static, since it
is not used outside of this translation module.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agopci: pciinfo_header can be static
Vladimir Oltean [Fri, 17 Sep 2021 12:11:24 +0000 (15:11 +0300)]
pci: pciinfo_header can be static

To avoid W=1 build warnings, declare this function as static, since it
is not used outside of this translation module.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agopci: pci_header_show can be static
Vladimir Oltean [Fri, 17 Sep 2021 12:11:23 +0000 (15:11 +0300)]
pci: pci_header_show can be static

To avoid W=1 build warnings, declare this function as static, since it
is not used outside of this translation module.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agopci: pci_bar_show can be static
Vladimir Oltean [Fri, 17 Sep 2021 12:11:22 +0000 (15:11 +0300)]
pci: pci_bar_show can be static

To avoid W=1 build warnings, declare this function as static, since it
is not used outside of this translation module.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agopci: include pci_internal.h inside pci_auto.c
Vladimir Oltean [Fri, 17 Sep 2021 12:11:21 +0000 (15:11 +0300)]
pci: include pci_internal.h inside pci_auto.c

To avoid a build warning with W=1, provide a function prototype for
dm_pciauto_prescan_setup_bridge, which is a non-static function whose
definition is inside pci_auto.c.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agopci: provide prototype for pci_skip_dev outside of #if defined(CONFIG_DM_PCI_COMPAT)
Vladimir Oltean [Fri, 17 Sep 2021 12:11:20 +0000 (15:11 +0300)]
pci: provide prototype for pci_skip_dev outside of #if defined(CONFIG_DM_PCI_COMPAT)

The weak definition of pci_skip_dev from drivers/pci/pci_common.c is not
under CONFIG_DM_PCI_COMPAT, and that definition needs a previous
function prototype declaration to avoid W=1 build warnings.

That prototype is not available due to it being under CONFIG_DM_PCI_COMPAT,
so move it outside of that preprocessor block.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agortc: rx8025: revise single register write to use offset
Mathew McBride [Fri, 17 Sep 2021 06:46:04 +0000 (06:46 +0000)]
rtc: rx8025: revise single register write to use offset

Writing of individual registers was not functioning
correctly as a 0 'offset' byte under DM-managed
I2C was being appended in front of register we
wanted to access.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
3 years agortc: rx8025: set date in a single i2c transaction
Mathew McBride [Fri, 17 Sep 2021 06:46:03 +0000 (06:46 +0000)]
rtc: rx8025: set date in a single i2c transaction

The RX8025/RX8035 does not like having it's time registers
set byte-by-byte in separate I2C transactions.

From the note at the top of the file, it appears
target-dependent workarounds have been used in the
past for this.

Resolve this by setting the time registers in a single
I2C transaction.

As part of this, also ensure the '24/12' flag in the RTC
is reset before writing the date (instead of after), otherwise
the RX8035 will clear the seconds and minutes registers.

Tested on Traverse Ten64 (NXP LS1088A) with RX8035.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
3 years agortc: rx8025: add support for EPSON RX8035.
Mathew McBride [Fri, 17 Sep 2021 06:46:02 +0000 (06:46 +0000)]
rtc: rx8025: add support for EPSON RX8035.

The RX8035 is a newer model from EPSON which is
very similar in operation to the RX8025.

The changes mirror similar ones that will be
in Linux 5.15:
https://lore.kernel.org/all/20210709044518.28769-2-matt@traverse.com.au/

The UBOOT_DRIVER ID has also been corrected, previously
it declared itself as rx8010sj_rtc which is a different driver.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
3 years agortc: rx8025: drop non-DM support
Mathew McBride [Fri, 17 Sep 2021 06:46:01 +0000 (06:46 +0000)]
rtc: rx8025: drop non-DM support

A search of the tree showed there is only one user
of this driver (soon to be two) - board/socrates

The second user will be the Traverse Ten64 board.

Both these boards have DM_RTC.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
3 years agoARM: dts: ast2600: Make WDT by default disabled
Chia-Wei Wang [Thu, 16 Sep 2021 06:10:09 +0000 (14:10 +0800)]
ARM: dts: ast2600: Make WDT by default disabled

The WDT devices described in the general .dtsi file
should be marked as "disabled" by default.

A WDT should be then enabled in the board specific
.dts file on demands.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
3 years agoarm: ti: k3: Resync dts files and bindings with Linux Kernel v5.14
Tom Rini [Fri, 10 Sep 2021 21:37:43 +0000 (17:37 -0400)]
arm: ti: k3: Resync dts files and bindings with Linux Kernel v5.14

This resyncs the dts files for all of the currently in-tree K3
platforms, along with relevant bindings, with the v5.14 Linux Kernel
release.  Of note are that the main-navss/mcu-navss nodes were renamed
to main_navss / mcu_navss and so the u-boot.dtsi files needed to be
updated to match.

Tested on j721e_evm and am65x_evm.

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agodt-bindings: pinctrl: k3: Synchronize with v5.14 kernel
Nishanth Menon [Tue, 31 Aug 2021 18:12:24 +0000 (13:12 -0500)]
dt-bindings: pinctrl: k3: Synchronize with v5.14 kernel

Synchronize with the upstream version as of v5.14 kernel tag

Signed-off-by: Nishanth Menon <nm@ti.com>
3 years agoMerge branch '2021-10-01-assorted-removal-and-migration' into next
Tom Rini [Sat, 2 Oct 2021 19:47:28 +0000 (15:47 -0400)]
Merge branch '2021-10-01-assorted-removal-and-migration' into next

- Remove the last non-CONFIG_DM boards, and their related unused code.
- Finish a few partial migrations to Kconfig, and remove some redundant
  serial related code.

3 years agoserial: Remove extraneous SYS_MALLOC_F check
Tom Rini [Mon, 13 Sep 2021 21:24:54 +0000 (17:24 -0400)]
serial: Remove extraneous SYS_MALLOC_F check

We enforce that DM_SERIAL will have SYS_MALLOC_F enabled and so
SYS_MALLOC_F_LEN will have a value.  Remove the build-time check.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoserial: Use the default CONFIG_SYS_BAUDRATE_TABLE in more platforms
Tom Rini [Mon, 13 Sep 2021 21:24:53 +0000 (17:24 -0400)]
serial: Use the default CONFIG_SYS_BAUDRATE_TABLE in more platforms

A number of platforms are still defining CONFIG_SYS_BAUDRATE_TABLE to
the fallback default of "{ 9600, 19200, 38400, 57600, 115200 }", but
with varying whitespace, or were introduced after the default fallback
was added.  Use the default table here.

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoConvert CONFIG_BAUDRATE to Kconfig
Tom Rini [Mon, 13 Sep 2021 21:24:52 +0000 (17:24 -0400)]
Convert CONFIG_BAUDRATE to Kconfig

This converts the following to Kconfig:
   CONFIG_BAUDRATE

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agokgdb: Remove unused serial related options
Tom Rini [Mon, 13 Sep 2021 21:24:51 +0000 (17:24 -0400)]
kgdb: Remove unused serial related options

We have a few CONFIG options for KGDB that are not referenced, remove
them.

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoppc: Remove MPC8349EMDS board and ARCH_MPC8349 support
Tom Rini [Thu, 9 Sep 2021 11:54:53 +0000 (07:54 -0400)]
ppc: Remove MPC8349EMDS board and ARCH_MPC8349 support

This board has not been converted to CONFIG_DM by the deadline.
Remove it.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoarm: Remove bg0900 board
Tom Rini [Thu, 9 Sep 2021 11:54:51 +0000 (07:54 -0400)]
arm: Remove bg0900 board

This board has not been converted to CONFIG_DM by the deadline.
Remove it.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoarm: Remove zmx25 board and ARCH_MX25
Tom Rini [Thu, 9 Sep 2021 11:54:50 +0000 (07:54 -0400)]
arm: Remove zmx25 board and ARCH_MX25

This board has not been converted to CONFIG_DM by the deadline.
Remove it.  As this is the last ARCH_MX25 platform, remove those
references as well.

Cc: Matthias Weisser <weisserm@arcor.de>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoarm: Remove aspenite board
Tom Rini [Thu, 9 Sep 2021 11:54:49 +0000 (07:54 -0400)]
arm: Remove aspenite board

This board has not been converted to CONFIG_DM by the deadline.
Remove it.  As this is the last armada100 platform, remove that support
as well.

Cc: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoarm: Remove flea3 board
Tom Rini [Tue, 14 Sep 2021 13:09:31 +0000 (09:09 -0400)]
arm: Remove flea3 board

This board has not been converted to CONFIG_DM by the deadline.
Remove it.  As this is the last mx35 platform, remove that support as
well.

Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefano Babic <sbabic@denx.de>