Ang, Chee Hong [Thu, 20 Dec 2018 02:35:12 +0000 (18:35 -0800)]
arm: socfpga: stratix10: Add generic FPGA reconfig mailbox API for S10
Add a generic mailbox API for FPGA reconfig status which can be
called by others. This new function accepts 2 different mailbox
commands: CONFIG_STATUS or RECONFIG_STATUS.
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
Neil Armstrong [Mon, 17 Dec 2018 09:26:16 +0000 (10:26 +0100)]
arm: dts: s400: Fix status for eMMC and SDIO ports
Under U-boot, the WiFi SDIO Module should be disabled and the
eMMC modules should be enabled, so this patch adds an s400-u-boot.dtsi
include file specific for U-Boot that will be included by the build system.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Paul Burton [Sun, 16 Dec 2018 22:25:23 +0000 (19:25 -0300)]
mips: jz47xx: Add Creator CI20 platform
Add support for the Creator CI20 platform based on the JZ4780 SoC.
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Marek Vasut <marex@denx.de>
Paul Burton [Sun, 16 Dec 2018 22:25:22 +0000 (19:25 -0300)]
mips: jz47xx: Add JZ4780 SoC support
Add initial support for the Ingenic JZ47xx MIPS SoC.
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Marek Vasut <marex@denx.de>
Paul Burton [Sun, 16 Dec 2018 22:25:21 +0000 (19:25 -0300)]
mips: Add SPL header
Add header with SPL boot mode and type definitions.
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Paul Burton [Sun, 16 Dec 2018 22:25:20 +0000 (19:25 -0300)]
mmc: Add JZ47xx SD/MMC controller driver
Add driver for the JZ47xx MSC controller.
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Marek Vasut <marex@denx.de>
Paul Burton [Sun, 16 Dec 2018 22:25:19 +0000 (19:25 -0300)]
misc: Add JZ47xx efuse driver
Add driver for the efuse block in the JZ47xx SOC.
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Marek Vasut <marex@denx.de>
MIPS: remove local_irq_[save|restore] from CP0 macros
With moving write_on_tlb() to arch/mips/include/asm/mipsregs.h
there are now compiler warnings when some generic code includes
asm/io.h. This happens for example when enabling OF live tree.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Gregory CLEMENT [Tue, 9 Oct 2018 12:08:42 +0000 (14:08 +0200)]
gpio: mscc-bitbang-spi: Add a simple gpio driver for bitbgang spi
The VCore III SoCs such as the Luton but also the Ocelot can remap an SPI
flash directly in memory. However, for writing in the flash the
communication has to be done by software.
Each of the signal used for the SPI are exposed in a single register. In
order to be able to use the soft-spi driver, the management of this pin
is done through this simple gpio driver.
Even if the main purpose of this driver is to be used by soft-spi, it can
still be used as a normal gpio driver but with limitation: for example
the first pin can't be used as output.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Gregory CLEMENT [Sat, 8 Dec 2018 08:59:01 +0000 (09:59 +0100)]
pinctrl: mscc: Add gpio and pinctrl driver for MSCC MIPS SoCs (VcoreIII based)
This driver supports the pin and gpio controller found in the Ocelot and
Luton SoCs.
The driver was inspired from the pinctrl driver in Linux, but was
simplified and was modified to allow supporting an other SoCs (Luton).
For Ocelot and Luton the controller is the same, only the pins to program
differ.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
[changed to only descend into mscc/ dependent on CONFIG_PINCTRL_MSCC] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Gregory CLEMENT [Tue, 9 Oct 2018 12:14:07 +0000 (14:14 +0200)]
DW SPI: Allow to overload the management of the external CS
On some platforms, as the Ocelot ones, when wanting to control the CS
through software, it is not possible to do it through the GPIO
controller. Indeed, this signal is managed through a dedicated range of
registers inside the SoC..
By declaring the external_cs_manage function as weak, it is possible to
manage the CS at platform level and then using the appropriate registers.
Stefan Roese [Tue, 18 Dec 2018 09:27:15 +0000 (10:27 +0100)]
mips: mt76xx: linkit/gardena: Don't use CONFIG_OF_EMBED
Building with CONFIG_OF_EMBED generates build warnings, as it should
only be used for debugging purposes. So let's move all MT7688 targets to
CONFIG_OF_SEPARATE instead with this patch.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Stefan Roese [Tue, 18 Dec 2018 09:27:14 +0000 (10:27 +0100)]
mips: mt76xx: Flush d-cache in arch_misc_init() to solve d-cache issues
It has been noticed, that sometimes the d-cache is not in a
"clean-state" when U-Boot is running on MT7688. This was detected when
using the ethernet driver (which uses d-cache) and a TFTP command does
not complete. Flushing the complete d-cache (again?) here seems to fix
this issue.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Remove all interrupt nodes that cause warnings regarding a missing
interrupt parent. There are no interrupt controller nodes defined
and the device trees don't match the ones in Linux anymore.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Rick Chen [Tue, 18 Dec 2018 03:02:27 +0000 (11:02 +0800)]
riscv: configs: Rename ax25-ae350 defconfig
Remove cpu name from the defconfig naming.
Because other cpus maybe run on AE350 platform.
So only use platfrom name in defconfig naming
will be better.
Also sync MAINTAINERS:
Rename
a25-ae350_32_defconfig as ae350_rv32_defconfig
ax25-ae350_64_defconfig as ae350_rv64_defconfig
Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Wed, 12 Dec 2018 14:12:45 +0000 (06:12 -0800)]
riscv: Save boot hart id to the global data
At present the hart id passed via a0 in the U-Boot entry is saved
to s0 at the beginning but does not preserve later. Save it to the
global data structure so that it can be used later.
Bin Meng [Wed, 12 Dec 2018 14:12:39 +0000 (06:12 -0800)]
riscv: Add indirect stringification to csr_xxx ops
With current csr_xxx ops, we cannot pass a macro to parameter
'csr', hence we need add another level to allow the parameter
to be a macro itself, aka indirect stringification.
Bin Meng [Wed, 12 Dec 2018 14:12:38 +0000 (06:12 -0800)]
riscv: Update supports_extension() to use desc from cpu driver
This updates supports_extension() implementation to use the desc
string from the cpu driver whenever possible, which avoids the
reading of misa CSR for S-mode U-Boot.
Bin Meng [Wed, 12 Dec 2018 14:12:36 +0000 (06:12 -0800)]
riscv: Add CSR numbers
The standard RISC-V ISA sets aside a 12-bit encoding space for up
to 4096 CSRs. This adds all known CSR numbers as defined in the
RISC-V Privileged Architecture Version 1.10.
Bin Meng [Wed, 12 Dec 2018 14:12:30 +0000 (06:12 -0800)]
riscv: Add a SYSCON driver for SiFive's Core Local Interruptor
This adds U-Boot syscon driver for SiFive's Core Local Interruptor
(CLINT). The CLINT block holds memory-mapped control and status
registers associated with software and timer interrupts.
This driver implements the riscv_get_time() API as required by
the generic RISC-V timer driver, as well as some other APIs that
are needed for handling IPI.
Bin Meng [Wed, 12 Dec 2018 14:12:28 +0000 (06:12 -0800)]
riscv: ax25: Hide the ax25-specific Kconfig option
There is no need to expose RISCV_NDS to the Kconfig menu as it is
an ax25-specific option. Introduce a dedicated Kconfig option for
the cache ops of ax25 platform and use that to guard the cache ops.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
Bin Meng [Wed, 12 Dec 2018 14:12:27 +0000 (06:12 -0800)]
timer: Add generic driver for RISC-V privileged architecture defined timer
RISC-V privileged architecture v1.10 defines a real-time counter,
exposed as a memory-mapped machine-mode register - mtime. mtime must
run at constant frequency, and the platform must provide a mechanism
for determining the timebase of mtime. The mtime register has a
64-bit precision on all RV32, RV64, and RV128 systems.
Different platform may have different implementation of the mtime
block hence an API riscv_get_time() is required by this driver for
platform codes to hide such implementation details. For example,
on some platforms mtime is provided by the CLINT module, while on
some other platforms a simple 'rdtime' can be used to get the timer
counter.
With this timer driver the U-Boot timer functionalities like delay
works correctly now.
Lukas Auer [Wed, 12 Dec 2018 14:12:23 +0000 (06:12 -0800)]
riscv: add Kconfig entries for the code model
RISC-V has two code models, medium low (medlow) and medium any (medany).
Medlow limits addressable memory to a single 2 GiB range between the
absolute addresses -2 GiB and +2 GiB. Medany limits addressable memory
to any single 2 GiB address range.
By default, medlow is selected for U-Boot on both 32-bit and 64-bit
systems.
The -mcmodel compiler flag is selected according to the Kconfig
configuration.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
[bmeng: adjust to make medlow the default code model for U-Boot] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
Sam Protsenko [Tue, 11 Dec 2018 16:20:21 +0000 (18:20 +0200)]
arm: ti: boot: Increase system partition size
Android code base is growing, so since Android "Pie" the size of
system.img grew up to be about 740 MiB. Let's increase system.img to
1 GiB to accommodate for those changes and leave some margin for future
changes. We don't want to make it more than 1 GiB, because we should
keep userdata partition big enough (for user files, like media etc.),
and eMMC size on BeagleBoard-X15 is only 3.5 GiB.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Acked-by: Praneeth Bajjuri <praneeth@ti.com>
Chris Packham [Fri, 14 Dec 2018 22:35:54 +0000 (11:35 +1300)]
Makefile: output migration warnings to stderr
Output the device model migration warnings to stderr. This allows tools
like buildman to pick them up rather than suppressing them along with
the normal build output on stdout.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Stefano Babic [Mon, 17 Dec 2018 10:02:00 +0000 (11:02 +0100)]
Restore compatibility of image type IDs
Commit a2b96ece5be146f4995d737f047e5bbb76079b8f breaks the enumeration
of the Image Types. New image types can be appended, but they cannot be
inserted in the list else backward compatibility is broken.
This restores the images types as before 2018.11 and move i.MX8 related
images at the end.
Signed-off-by: Robert Berger <robert.berger@ReliableEmbeddedSystems.com> Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 15 Dec 2018 22:47:28 +0000 (17:47 -0500)]
Merge branch '2018-12-15-master-imports'
- Introduce tools-only build for host tools
- Bugfixes to poplar, syscon and the hashtable, a tee return code
- Fix a warning on gcc-8 by reworking part of mtk_image to be not unsafe
wrt strings.
- serial_stm32 reset support
Kever Yang [Fri, 14 Dec 2018 01:37:12 +0000 (09:37 +0800)]
rockchip: rk3288-evb: dts: remove 'vmmc' from emmc node
This is a sync with kernel mainline dts.
The U-Boot eMMC does not need to care about the power for Rockchip
SoCs, because if the board is using eMMC, the power will default on
(for bootrom), so the 'vmmc', 'vqmmc' is only useful for SD in U-Boot.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
vcc5v0_host and usbhub_enable share gpio4 RK_PA3,
which is a problem during probing (the second probe
will trigger a -EBUSY, when trying to get the gpio handle).
An analysis of the situation shows, that both regulators
are actually describing the same supply.
This patch removes the (currenlty not successful probing)
regulator vcc5v0_host from the DTS and adds the pinctrl-*
setting to usbhub_enable.
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Phiilipp Tomsich <philipp.tomsich@theobroma-systems.com>
projects / u-boot.git / log
![6 years agoMIPS: remove local_irq_[save|restore] from CP0 macros](/img/static/git-favicon.png?p=u-boot.git;a=commit;h=a0abb52c5a5b1de522380984bb9429ee973b1f8e){kind=link}
