Patrick Delaunay [Mon, 15 Jan 2024 14:05:51 +0000 (15:05 +0100)]
smt32mp: add setup_mac_address for stm32mp25
Add a function setup_mac_address() to update the MAC address from the
default location in OTP for stm32mp2 platform.
The max number of OTP for MAC address is increased to 8 for STM32MP25,
defined with get_eth_nb() and checked in setup_mac_address.
The MAC address FF:FF:FF:FF:FF:FF, the broadcast ethaddr, is a invalid
value used for unused MAC address slot in OTP, for example for board
with STM32MP25x part number allows up to 5 ethernet ports but it is not
supported by the hardware, without switch; the associated variable
"enetaddr%d" is not created.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Patrick Delaunay [Mon, 15 Jan 2024 14:05:46 +0000 (15:05 +0100)]
stm32mp: bsec: add driver data
Add driver data in BSEC driver to test presence of OP-TEE TA,
mandatory for STM32MP13 family and prepare the support of new device
with more OTP than 95.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Patrick Delaunay [Mon, 15 Jan 2024 14:05:44 +0000 (15:05 +0100)]
arm64: dts: st: add bsec support to stm32mp25
Add BSEC support to STM32MP25 SoC family with SoC information:
- RPN = Device part number (BSEC_OTP_DATA9)
- PKG = package data register (Bits 2:0 of BSEC_OTP_DATA122)
Tom Rini [Thu, 18 Jan 2024 16:38:25 +0000 (11:38 -0500)]
Revert "test: hush: dollar: fix bugous behavior"
What we were doing here amounts to simplifying the code for the new hush
parser, and the workarounds are required when using the old one. As we
have returned to having the old parser be default for now, we must undo
this so that the test passes again.
Tom Rini [Thu, 18 Jan 2024 14:07:25 +0000 (09:07 -0500)]
Revert "cmd: Set modern hush as default shell"
Currently at least two SoC families are able to cause a crash using
their regular boot scripts, with the new parser. For now, revert to the
old parser as default.
Tom Rini [Wed, 17 Jan 2024 22:12:36 +0000 (17:12 -0500)]
test: test_trace.py: Have trace-cmd report always use -l
With newer versions of trace-cmd the report subcommand will have
different output from before if we do or do not pass -l. However, with
the -l flag passed our put is consistent here. This updates our regular
expressions and comments for this as well now.
QEMU commit 0c7ffc977195 ("hw/net: cadence_gem: Fix MDIO_OP_xxx values")
is needed to fix the Ethernet PHY driver used by the emulated SiFive
Unleashed Board emulation.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tom Rini [Wed, 17 Jan 2024 14:27:43 +0000 (09:27 -0500)]
Merge tag 'xilinx-for-v2024.04-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2024.04-rc1-v2
xilinx:
- Enable NFS, WGET, DNS and BLKMAP by default
zynqmp:
- Support new power-management node
- Remove multiple blank lines from DTSes
- Wire multiboot with DFU infrastructure
- Fix i2c-gpio pinctrl group name
- SOM DT changes (phy on kd240, kv260 cleanups
- Cleanup i2c bus on zcu1285
- DT cleanup (fix node names not to use _)
- Fix USB interrupts
- Cleanup zcu100 DT
- Add support for kaslr-seed
Tom Rini [Wed, 17 Jan 2024 14:27:23 +0000 (09:27 -0500)]
Merge tag 'efi-2024-04-rc1-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Documentation:
* add generated index to table of contents
* create index entries for commands
* update Python packages used to build the documentation
* fix typos in dfu documentation
- Add more pytests to exercise functionality on real hardware, cleanup
and add tests around "cp"/memmove, add phyCORE-AM62x and Phytium
Pe2201 platforms, Nuvoton NPCM BMC reset driver and improve QEMU
SMBIOS support
The first sentence is half-way true; the macro is always defined, but
has the value 0 or 1.
The second is outright false. A lot of code guarded by
MEM_SUPPORT_64BIT_DATA uses a "ulong" to store values, so if
sizeof(long) is not 8, that code would probably compile, but not work
at all as expected.
It would probably be possible to make all such code explicitly use u64
and thus make it work on 32 bit targets, but until that is done, do
not pretend that it's ok to override the automatic value of
MEM_SUPPORT_64BIT_DATA.
AKASHI Takahiro [Wed, 17 Jan 2024 04:39:44 +0000 (13:39 +0900)]
fs: remove explicit efi configuration dependency
Now it is clear that the feature actually depends on efi interfaces,
not "bootefi" command. efi_set_bootdev() will automatically be nullified
if necessary efi component is disabled.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Now it is clear that the feature actually depends on efi interfaces,
not "bootefi" command. efi_set_bootdev() will automatically be nullified
if necessary efi component is disabled.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
AKASHI Takahiro [Wed, 17 Jan 2024 04:39:41 +0000 (13:39 +0900)]
efi_loader: split unrelated code from efi_bootmgr.c
Some code moved from cmd/bootefi.c is actually necessary only for "bootefi
<addr>" command (starting an image manually loaded by a user using U-Boot
load commands or other methods (like JTAG debugger).
The code will never been opted out as unused code by a compiler which
doesn't know how EFI boot manager is implemented. So introduce a new
configuration, CONFIG_EFI_BINARY_EXEC, to enforce them opted out
explicitly.
We want to override the Sphinx theme only partially. So we need to
import the Sphinx theme.css. Cf.
https://docs.readthedocs.io/en/stable/guides/adding-custom-css.html
We also need to import the pygments.css for syntax highlighing.
Use sans-serif for body.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Newer versions of sphinx_rtd_theme require to add sphinx_rtd_theme to the
list of extensions. Cf.
https://github.com/readthedocs/readthedocs.org/pull/9654
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Oliver Faso [Sun, 14 Jan 2024 13:18:19 +0000 (14:18 +0100)]
docs/sphinx: Explicitly convert Sphinx paths to str
Sphinx 7.2+ is switching to using pathlib.Path
instead of str to represent paths. This fixes the
current deprecation warnings and eventual breakage.
This conversion will be a no-op when using older
Sphinx versions.
Signed-off-by: Oliver Faso <erer1243@gmail.com> Tested-by: Akira Yokosawa <akiyks@gmail.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Link: https://lore.kernel.org/r/20230910040811.53046-1-erer1243@gmail.com Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Create a ft_board_setup() api that gets called as part
of bootm/booti before jumping to kernel. In this
ft_board_setup() callback that will inspect the DTB
and insert the device tree blob with the "kaslr-seed" property.
cmd/command.c: relax length check in cmd_get_data_size()
Just check that the length is at least 2. This allows passing strings
like ".b", which can be convenient when constructing
tests (i.e. parametrizing the suffix used).
cmd/command.c: constify "arg" argument of cmd_get_data_size()
This function obviously does not and must not modify "arg". Change the
prototype to allow passing an argument of type "const char*" without
requiring a cast.
There's no 'mv' shell command for handling overlapping src and dst
regions, and there's no point introducing one, when we can just make
the existing 'cp' command DTRT in all cases. memmove() should at most
be a few instructions more then memcpy() (to detect the appropriate
direction to do the copy), which is of course completely in the noise
with all the string processing that a shell command does.
Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Love Kumar [Wed, 3 Jan 2024 10:29:42 +0000 (15:59 +0530)]
test/py: memtest: Add tests for mtest command
Add the following memory tests:
memtest_negative - To test mtest command by providing incorrect inputs
memtest_ddr - To test memory write-read-comparision for DDR memory
Jim Liu [Wed, 3 Jan 2024 07:29:33 +0000 (15:29 +0800)]
reset: npcm: Add support for Nuvoton NPCM BMC family
Add reset controller driver for Nuvoton BMCs.
The npcm reset driver not only supports reset each module reset
but setting initial value of reset Control Registers.
Love Kumar [Tue, 2 Jan 2024 06:47:07 +0000 (12:17 +0530)]
test/py: i2c: Add tests for i2c command
Add below test cases for i2c commands:
i2c_bus - To show i2c bus info,
i2c_dev - To set or show the current bus,
i2c_probe - To probe the i2c device,
i2c_eeprom - To test i2c eeprom device,
i2c_probe_all_buses - To list down all the buses and probes it
Love Kumar [Tue, 2 Jan 2024 06:44:35 +0000 (12:14 +0530)]
test/py: mii: Add tests for mii command
Add below test cases for mii commands:
mii_info -To display MII PHY info
mii_list - To list MII devices
mii_set_device - To set MII device
mii_read - To reads register from MII PHY address
mii_dump - To display data from MII PHY address
Signed-off-by: Love Kumar <love.kumar@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com>
TracyMg_Li [Mon, 25 Dec 2023 03:21:34 +0000 (11:21 +0800)]
ARM add initial support for the Phytium Pe2201 Board.
Add pe2201 platform code and the device tree of pe2201 platform board.
The initial support comprises the UART and PCIe.
Signed-off-by: TracyMg_Li <TracyMg_Li@outlook.com>
Changes since v1:
fix space corrupt.
Changes since v2:
switch to bootstd and text environment.
Changes since v3:
add environment variables.
next_header() and get_next_header() only differ in how the const attribute
is used. One function taking a const parameter and returning a non-const is
good enough.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Love Kumar [Tue, 19 Dec 2023 12:20:51 +0000 (17:50 +0530)]
test/py: mdio: Add tests for mdio command
Add below test cases for mdio commands:
mdio_list - To list MDIO buses
mdio_read - To read PHY's register at <devad>.<reg>
mdio_write - To write PHY's register at <devad>.<reg>
Signed-off-by: Love Kumar <love.kumar@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 16 Jan 2024 14:51:16 +0000 (09:51 -0500)]
Merge tag 'qcom-2024.04-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-snapdragon
Qualcomm architecture changes:
* Move clock and pinctrl drivers out of mach-snapdragon
* Various clock driver improvements
* Convert PMIC power/reset key driver to use the button API
* Preparetory work for migrating to upstream DT
Caleb Connolly [Mon, 15 Jan 2024 18:03:17 +0000 (18:03 +0000)]
sandbox_flattree: enable button support
sandbox_flattree enables QCOM_PMIC_GPIO which now depends on BUTTON. As
a result the button tests now get run, but fail because the ADC and GPIO
button drivers aren't enabled.
Enable them to run the tests for sandbox_flattree.
Reported-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Tue, 5 Dec 2023 13:46:54 +0000 (13:46 +0000)]
pmic: qcom: dont use dev_read_addr to get USID
Linux DTs stuff a value indicating if the USID is a USID or a GSID in the
reg property, the Linux SPMI driver then reads the two address cells
separately. U-boot's dev_read_addr() doesn't know how to handle this, so
use ofnode_read_u32_index() to get just the USID.
The Qcom pmic driver doesn't have support for GSID handling, so just
ignore the second value for now.
Caleb Connolly [Tue, 5 Dec 2023 13:46:48 +0000 (13:46 +0000)]
mach-snapdragon: switch to PMIC button driver
The PMIC button driver is a much better representation of the hardware
here, adjust the boards to use upstream DT and the PMIC button driver
instead of exposing the buttons as GPIOs and relying on the GPIO-button
driver.
Qualcomm PMICs include a "pon" function which handles two buttons, the
power button and "resin" button (usually volume down). Introduce a new
driver following upstream Linux DT to enable these and map them to Enter
and Down respectively to enable use in boot menus.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
priv->pid is uint32_t, but dev_read_addr() returns a uint64_t on arm64,
with the upper bits being used for error codes. Do error checking before
downcasting to u32 to prevent errors being silently ignored.
Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Tue, 14 Nov 2023 12:51:11 +0000 (12:51 +0000)]
serial: msm-geni: don't rely on parent misc device
commit 1b15483deb3f ("misc: add Qualcomm GENI SE QUP device driver")
introduced support for platform-specific oversampling values, necessary
to configure the UART clocks on all platforms at runtime. However it
relies in probing a parent device. Despite the DM_FLAG_PRE_RELOC flag,
this is not done consistently during boot.
Instead, take another approach by relying on ofnode_ helpers to read the
serial engine base address and do the read directly. This fixes early
UART on boards with a non-default oversampling rate.
Caleb Connolly [Tue, 14 Nov 2023 12:55:42 +0000 (12:55 +0000)]
pinctrl: qcom: make compatible with linux DTs
The pinctrl and GPIO drivers are currently heavily incompatible with
upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at
it's own address. Introduce support for these by allowing the soc driver
to specify per-pin register offsets similarly to the Linux driver.
Adjust the GPIO driver to handle these too, and finally enable support
for all pins with the same numbering as used in Linux.
Caleb Connolly [Tue, 14 Nov 2023 12:55:40 +0000 (12:55 +0000)]
pinctrl: qcom: move out of mach-snapdragon
Move the Qualcomm pinctrl drivers out of mach-snapdragon and over to the
rest of the pinctrl drivers, adjust the drivers so that support for each
platform can be enabled/disabled individually and introduce platform
specific configuration options.
Caleb Connolly [Tue, 7 Nov 2023 12:41:05 +0000 (12:41 +0000)]
clk/qcom: fix rcg divider value
The RCG divider field takes a value of (2*h - 1) where h is the divisor.
This allows fractional dividers to be supported by calculating them at
compile time using a macro.
However, the clk_rcg_set_rate_mnd() function was also performing the
calculation. Clean this all up and consistently use the F() macro to
calculate these at compile time and properly support fractional divisors.
Additionally, improve clk_bcr_update() to timeout with a warning rather
than hanging the board, and make the freq_tbl struct and helpers common
so that they can be reused by future platforms.
Caleb Connolly [Tue, 7 Nov 2023 12:41:03 +0000 (12:41 +0000)]
clk/qcom: use function pointers for enable and set_rate
Currently, it isn't possible to build clock drivers for more than one
platform due to how the msm_enable() and msm_set_rate() callbacks are
implemented.
Extend qcom_clk_data to include function pointers for these and convert
all platforms to use them.
Previously, clock drivers relied on include/configs/<board.h> to include the
board specific sysmap header, however as most of the header contents are clock
driver related, import the contents directly into each clock driver and
remove the header. The only exception here is the dragonboard820c board file
which includes some pinctrl macros, those are also inlined.
Konrad Dybcio [Tue, 7 Nov 2023 12:41:01 +0000 (12:41 +0000)]
clk/qcom: handle resets and clocks in one device
Qualcomm's clock controller blocks actually do much more than it
says on the tin.. They provide clocks, resets and power domains.
Currently, U-Boot requires one to spawn 2 separate devices for
controlling clocks and resets, both spanning the same register space.
Refactor the code to make it work with just a single DT node, making
it compatible with upstream Linux bindings and dropping the dedicated
reset driver in favour of including it in the clock driver.
Heavily inspired by Renesas code for a similar hw block.
[caleb: moved drivers to clk/qcom, added reset driver and adjusted bind
logic. Imported qcom,gcc-ipq4019.h from Linux]
Caleb Connolly [Tue, 7 Nov 2023 12:40:59 +0000 (12:40 +0000)]
clk/qcom: move from mach-snapdragon
Clock drivers don't belong here, move them to the right place and
declutter mach-snapdragon a bit.
To de-couple these drivers from specific "target" platforms, add
additional config options to enable each clock driver gated behind a
common CLK_QCOM option and enable them by default for the respective
targets. This will make future work easier as we move towards a generic
Qualcomm target.
arm: xea: Add support for boot image source descriptor in SPL
We load two boot image source descriptor structures from last
two sectors in the SPI NOR flash and determine the boot source
for loading the kernel/DTB images, then adjust the boot order for
loading image from eMMC boot0 or boot1 partition.
Yannic Moog [Mon, 15 Jan 2024 09:31:41 +0000 (10:31 +0100)]
board: phytec: fix link error when disabling PHYTEC_SOM_DETECTION
Commit aa7858fe5e2e ("board: phytec: som_detection: move definitions to
source file") moved function definitions from header to source file.
Makefile however was not updated to unconditionally (from
[..]_SOM_DETECTION) build the imx8 and phytec som detection units.
Also remove unused includes that cause build failures on arm 32bit
boards. SoM detection shall support 32bit boards as well, but arch
specific code should not be included in the generic module.
Roger Quadros [Mon, 11 Dec 2023 11:45:59 +0000 (13:45 +0200)]
mtd: nand: omap_gpmc: Fix NAND in SPL for AM335x
AM335x uses a special driver "am335x_spl_bch.c" as SPL
NAND loader. This driver expects 1 sector at a time ECC
and doesn't work well with multi-sector ECC that was implemented in
commit 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction")
Additionally, the omap_elm driver does not support multi sector ECC and will
need more work and tests to get multi sector working correctly on all
platforms.
Switch back to 1 sector at a time read/ECC.
Fixes: 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction") Signed-off-by: Roger Quadros <rogerq@kernel.org> Tested-by: Enrico Leto <enrico.leto@siemens.com> Tested-by: Heiko Schocher <hs@denx.de> Link: https://lore.kernel.org/all/20231211114600.4414-2-rogerq@kernel.org/ Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
projects / u-boot.git / log
