From: Michael Walle <michael@walle.cc>
Date: Wed, 13 Oct 2021 16:14:07 +0000 (+0200)
Subject: arm: dts: ls1028a: move the SPI and eSDHC controller nodes into /soc
X-Git-Url: http://git.dujemihanovic.xyz/img/static/git-favicon.png?a=commitdiff_plain;h=fbddc2701d2e0faea8193c7bfc1d2c810f0f73a6;p=u-boot.git

arm: dts: ls1028a: move the SPI and eSDHC controller nodes into /soc

While inserting them into the new location, keep them sorted by the
register base offset just like in the linux kernel device tree.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
---

diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 6d80b32816..ecafa67d08 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -266,64 +266,6 @@
 		status = "disabled";
 	};
 
-	dspi0: dspi@2100000 {
-		compatible = "fsl,vf610-dspi";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x0 0x2100000 0x0 0x10000>;
-		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-		clock-names = "dspi";
-		clocks = <&clockgen 4 0>;
-		num-cs = <5>;
-		litte-endian;
-		status = "disabled";
-	};
-
-	dspi1: dspi@2110000 {
-		compatible = "fsl,vf610-dspi";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x0 0x2110000 0x0 0x10000>;
-		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-		clock-names = "dspi";
-		clocks = <&clockgen 4 0>;
-		num-cs = <5>;
-		little-endian;
-		status = "disabled";
-	};
-
-	dspi2: dspi@2120000 {
-		compatible = "fsl,vf610-dspi";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x0 0x2120000 0x0 0x10000>;
-		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-		clock-names = "dspi";
-		clocks = <&clockgen 4 0>;
-		num-cs = <5>;
-		little-endian;
-		status = "disabled";
-	};
-
-	esdhc0: esdhc@2140000 {
-		compatible = "fsl,esdhc";
-		reg = <0x0 0x2140000 0x0 0x10000>;
-		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-		big-endian;
-		bus-width = <4>;
-		status = "disabled";
-	};
-
-	esdhc1: esdhc@2150000 {
-		compatible = "fsl,esdhc";
-		reg = <0x0 0x2150000 0x0 0x10000>;
-		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
-		big-endian;
-		non-removable;
-		bus-width = <4>;
-		status = "disabled";
-	};
-
 	gpio0: gpio@2300000 {
 		compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
 		reg = <0x0 0x2300000 0x0 0x10000>;
@@ -484,5 +426,63 @@
 			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
+
+		dspi0: dspi@2100000 {
+			compatible = "fsl,vf610-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2100000 0x0 0x10000>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "dspi";
+			clocks = <&clockgen 4 0>;
+			num-cs = <5>;
+			litte-endian;
+			status = "disabled";
+		};
+
+		dspi1: dspi@2110000 {
+			compatible = "fsl,vf610-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2110000 0x0 0x10000>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "dspi";
+			clocks = <&clockgen 4 0>;
+			num-cs = <5>;
+			little-endian;
+			status = "disabled";
+		};
+
+		dspi2: dspi@2120000 {
+			compatible = "fsl,vf610-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2120000 0x0 0x10000>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "dspi";
+			clocks = <&clockgen 4 0>;
+			num-cs = <5>;
+			little-endian;
+			status = "disabled";
+		};
+
+		esdhc0: esdhc@2140000 {
+			compatible = "fsl,esdhc";
+			reg = <0x0 0x2140000 0x0 0x10000>;
+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+			big-endian;
+			bus-width = <4>;
+			status = "disabled";
+		};
+
+		esdhc1: esdhc@2150000 {
+			compatible = "fsl,esdhc";
+			reg = <0x0 0x2150000 0x0 0x10000>;
+			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+			big-endian;
+			non-removable;
+			bus-width = <4>;
+			status = "disabled";
+		};
 	};
 };