From: Kongyang Liu <seashell11234455@gmail.com>
Date: Sat, 20 Apr 2024 07:08:24 +0000 (+0800)
Subject: riscv: dts: sophgo: Add spi nor flash controller node
X-Git-Url: http://git.dujemihanovic.xyz/img/static/git-favicon.png?a=commitdiff_plain;h=df0bfaa136441dcb8c53b66e914366a2af9dfef8;p=u-boot.git

riscv: dts: sophgo: Add spi nor flash controller node

Add spi nor flash controller node for cv18xx SoCs

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---

diff --git a/arch/riscv/dts/cv1800b-milkv-duo.dts b/arch/riscv/dts/cv1800b-milkv-duo.dts
index f6ae8828f3..e7cc0e8bd1 100644
--- a/arch/riscv/dts/cv1800b-milkv-duo.dts
+++ b/arch/riscv/dts/cv1800b-milkv-duo.dts
@@ -46,6 +46,19 @@
 	no-sdio;
 };
 
+&spif {
+	status = "okay";
+
+	spiflash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <75000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		m25p,fast-read;
+	};
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
index 5e83ee1853..4b0143450e 100644
--- a/arch/riscv/dts/cv18xx.dtsi
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -66,6 +66,13 @@
 		#clock-cells = <0x0>;
 	};
 
+	spif_clk: spi-flash-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <300000000>;
+		clock-output-names = "spif_clk";
+		#clock-cells = <0>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		interrupt-parent = <&plic>;
@@ -220,6 +227,16 @@
 			status = "disabled";
 		};
 
+		spif: spi-nor@10000000 {
+			compatible = "sophgo,cv1800b-spif";
+			reg = <0x10000000 0x10000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&spif_clk>;
+			interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
 		plic: interrupt-controller@70000000 {
 			reg = <0x70000000 0x4000000>;
 			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;