From: Nishanth Menon Date: Thu, 27 Jul 2023 18:58:47 +0000 (-0500) Subject: doc: board: ti: j721e: Update with boot flow diagram X-Git-Url: http://git.dujemihanovic.xyz/img/static/git-favicon.png?a=commitdiff_plain;h=9e30ebc983df4ad789847a857a395a7ce898ff4e;p=u-boot.git doc: board: ti: j721e: Update with boot flow diagram Update the bootflow svg diagram instead of the ascii version Reviewed-by: Neha Malcom Francis Signed-off-by: Nishanth Menon --- diff --git a/doc/board/ti/img/boot_diagram_j721e.svg b/doc/board/ti/img/boot_diagram_j721e.svg new file mode 100644 index 0000000000..e61af5b767 --- /dev/null +++ b/doc/board/ti/img/boot_diagram_j721e.svg @@ -0,0 +1,2012 @@ + + + + + + + + + + + + + Cortex-R + + + + Cortex-R + + + + + + + + + + ROM + + + + ROM + + + + + + + + + Load and auth tiboot3.bin + + + + Load and auth t... + + + + + + + + + + Cortex-A + + + + Cortex-A + + + + + + + + + + Load system +config data + + + + Load system... + + + + + + + + + DDR Config + + + + DDR Config + + + + + + + + + Load tispl.bin + + + + Load tispl.bin + + + + + + + + + Start Cortex-A + + + + Start Cortex-A + + + + + + + + + Start DM + + + + Start DM + + + + + + + + + + Device Mgr + + + + Device Mgr + + + + + + + + + + Start Cortex-A + + + + Start Cort... + + + + + + + + + + + + + + + + + + + + + + + + + + + Aux f/w + + + + Aux f/w + + + + + + + + + + + Start TIFS + + + + Start TIFS + + + + + + + + + TIFS + + + + TIFS + + + + + + + + + + Load system config data + + + + Load syste... + + + + + + + + + Start TIFS + + + + Start TIFS + + + + + + + + + Load DM f/w + + + + Load DM f/w + + + + + + + + + + branch + + + + branch + + + + + + + + + + Release Reset + + + + Release Re... + + + + + + + + + TF-A + + + + TF-A + + + + + + + + + + OP-TEE + + + + OP-TEE + + + + + + + + + + Cortex A SPL + + + + Cortex A SPL + + + + + + + + + + U-Boot + + + + U-Boot + + + + + + + + + Load u-boot.img + + + + Load u-boot.img + + + + + + + + + Load Aux core f/w +(optional) + + + + Load Aux core f/w... + + + + + + + + + Start Aux core +(optional) + + + + Start Aux core... + + + + + + + + + + Release Reset + + + + Release Re... + + + + + + + + + + + + Cortex-R/M +C6x/C7x + + + + Cortex-R/M... + + + + + + + + + + TIFS/DMSC + + + + TIFS/DMSC + + + + + + + + + + ROM + + + + ROM + + + + + + + + + + Security Enclave Boot Processor + + + + Security Enclave Boot... + + + + + + + + + + Boot Loader +Processor + + + + Boot Loader... + + + + + + + + + + Main CPU + + + + Main CPU + + + + + + + + + + Auxiliary +Processor + + + + Auxiliary... + + + + + + + + + + H/w Seq: Reset rls + + + + H/w Seq: Reset rls + + + + + + + + + + Auth tiboot3.bin + + + + Auth tiboo... + + + + + + + + + + Release Reset + + + + Release Re... + + + + + + + + + Cortex-R SPL + + + + Cortex-R SPL + + + + + + + + + Load sysfw.itb + + + + Load sysfw.itb + + + + + + + + + + Auth TIFS + + + + Auth TIFS + + + + + + + Text is not SVG - cannot display + + + diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst index 637b42d7c6..16091ac445 100644 --- a/doc/board/ti/j721e_evm.rst +++ b/doc/board/ti/j721e_evm.rst @@ -34,96 +34,7 @@ Boot Flow: Boot flow is similar to that of AM65x SoC and extending it with remoteproc support. Below is the pictorial representation of boot flow: -.. code-block:: text - - +------------------------------------------------------------------------+-----------------------+ - | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | - +------------------------------------------------------------------------+-----------------------+ - | +--------+ | | | | - | | Reset | | | | | - | +--------+ | | | | - | : | | | | - | +--------+ | +-----------+ | | | - | | *ROM* |----------|-->| Reset rls | | | | - | +--------+ | +-----------+ | | | - | | | | : | | | - | | ROM | | : | | | - | |services| | : | | | - | | | | +-------------+ | | | - | | | | | *R5 ROM* | | | | - | | | | +-------------+ | | | - | | |<---------|---|Load and auth| | | | - | | | | | tiboot3.bin | | | | - | | | | +-------------+ | | | - | | | | : | | | - | | | | : | | | - | | | | : | | | - | | | | +-------------+ | | | - | | | | | *R5 SPL* | | | | - | | | | +-------------+ | | | - | | | | | Load | | | | - | | | | | sysfw.itb | | | | - | | Start | | +-------------+ | | | - | | System |<---------|---| Start | | | | - | |Firmware| | | SYSFW | | | | - | +--------+ | +-------------+ | | | - | : | | | | | | - | +---------+ | | Load | | | | - | | *SYSFW* | | | system | | | | - | +---------+ | | Config data | | | | - | | |<--------|---| | | | | - | | | | +-------------+ | | | - | | | | | DDR | | | | - | | | | | config | | | | - | | | | +-------------+ | | | - | | | | | Load | | | | - | | | | | tispl.bin | | | | - | | | | +-------------+ | | | - | | | | | Load R5 | | | | - | | | | | firmware | | | | - | | | | +-------------+ | | | - | | |<--------|---| Start A72 | | | | - | | | | | and jump to | | | | - | | | | | DM fw image | | | | - | | | | +-------------+ | | | - | | | | | +-----------+ | | - | | |---------|-----------------------|---->| Reset rls | | | - | | | | | +-----------+ | | - | | TIFS | | | : | | - | |Services | | | +-------------+ | | - | | |<--------|-----------------------|---->|*TF-A/OP-TEE*| | | - | | | | | +-------------+ | | - | | | | | : | | - | | | | | +-----------+ | | - | | |<--------|-----------------------|---->| *A72 SPL* | | | - | | | | | +-----------+ | | - | | | | | | Load | | | - | | | | | | u-boot.img| | | - | | | | | +-----------+ | | - | | | | | : | | - | | | | | +-----------+ | | - | | |<--------|-----------------------|---->| *U-Boot* | | | - | | | | | +-----------+ | | - | | | | | | prompt | | | - | | | | | +-----------+ | | - | | | | | | Load R5 | | | - | | | | | | Firmware | | | - | | | | | +-----------+ | | - | | |<--------|-----------------------|-----| Start R5 | | +-----------+ | - | | |---------|-----------------------|-----+-----------+-----|----->| R5 starts | | - | | | | | | Load C6 | | +-----------+ | - | | | | | | Firmware | | | - | | | | | +-----------+ | | - | | |<--------|-----------------------|-----| Start C6 | | +-----------+ | - | | |---------|-----------------------|-----+-----------+-----|----->| C6 starts | | - | | | | | | Load C7 | | +-----------+ | - | | | | | | Firmware | | | - | | | | | +-----------+ | | - | | |<--------|-----------------------|-----| Start C7 | | +-----------+ | - | | |---------|-----------------------|-----+-----------+-----|----->| C7 starts | | - | +---------+ | | | +-----------+ | - | | | | | - +------------------------------------------------------------------------+-----------------------+ +.. image:: img/boot_diagram_j721e.svg - Here DMSC acts as master and provides all the critical services. R5/A72 requests DMSC to get these services done as shown in the above diagram.