From: Dinesh Maniyam <dinesh.maniyam@intel.com>
Date: Tue, 31 May 2022 08:15:17 +0000 (+0800)
Subject: arm: dts: socfpga: stratix10: Add freeze controller node
X-Git-Url: http://git.dujemihanovic.xyz/img/static/git-favicon.png?a=commitdiff_plain;h=5474fb894cba4de1f8735e02155ca85d81af03de;p=u-boot.git

arm: dts: socfpga: stratix10: Add freeze controller node

The freeze controller is required for FPGA partial reconfig.
This node is disable on default.
Enable this node via u-boot fdt command when needed.

Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com>
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
---

diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
index 61df425f14..75a29045da 100755
--- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
@@ -2,7 +2,7 @@
 /*
  * U-Boot additions
  *
- * Copyright (C) 2019-2020 Intel Corporation <www.intel.com>
+ * Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
  */
 
 #include "socfpga_stratix10-u-boot.dtsi"
@@ -10,6 +10,15 @@
 /{
 	aliases {
 		spi0 = &qspi;
+		freeze_br0 = &freeze_controller;
+	};
+
+	soc {
+		freeze_controller: freeze_controller@f9000450 {
+			compatible = "altr,freeze-bridge-controller";
+			reg = <0xf9000450 0x00000010>;
+			status = "disabled";
+		};
 	};
 };