From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Date: Sat, 9 Oct 2021 20:41:04 +0000 (+0200)
Subject: verdin-imx8mm: fix ethernet
X-Git-Url: http://git.dujemihanovic.xyz/img/static/git-favicon.png?a=commitdiff_plain;h=5206f1ce0c137aab59ddafe89c2a1e8c87189d22;p=u-boot.git

verdin-imx8mm: fix ethernet

Turns out Microship (formerly Micrel) meanwhile integrated proper
support for the DLL setup on their KSZ9131. Unfortunately, this
conflicts with our previous board code doing that.
Fix this by getting rid of our board code and just relying on the
generic implementation relying on rgmii-id being used as phy-mode.

Fixes: commit c6df0e2ffdc4
       ("net: phy: micrel: add support for DLL setup on ksz9131")
Fixes: commit af2d3c91d877
       ("ARM: dts: imx8mm-verdin: Set PHY mode to RGMII-ID")
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
---

diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
index 76f4a1e209..1644f4b308 100644
--- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c
+++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
@@ -36,70 +36,6 @@ static int setup_fec(void)
 
 	return 0;
 }
-
-int board_phy_config(struct phy_device *phydev)
-{
-	int tmp;
-
-	switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
-	case PHY_ID_KSZ9031:
-		/*
-		 * The PHY adds 1.2ns for the RXC and 0ns for TXC clock by
-		 * default. The MAC and the layout don't add a skew between
-		 * clock and data.
-		 * Add 0.3ns for the RXC path and 0.96 + 0.42 ns (1.38 ns) for
-		 * the TXC path to get the required clock skews.
-		 */
-		/* control data pad skew - devaddr = 0x02, register = 0x04 */
-		ksz9031_phy_extended_write(phydev, 0x02,
-					   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
-					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
-					   0x0070);
-		/* rx data pad skew - devaddr = 0x02, register = 0x05 */
-		ksz9031_phy_extended_write(phydev, 0x02,
-					   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
-					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
-					   0x7777);
-		/* tx data pad skew - devaddr = 0x02, register = 0x06 */
-		ksz9031_phy_extended_write(phydev, 0x02,
-					   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
-					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
-					   0x0000);
-		/* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
-		ksz9031_phy_extended_write(phydev, 0x02,
-					   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
-					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
-					   0x03f4);
-		break;
-	case PHY_ID_KSZ9131:
-	default:
-		/* read rxc dll control - devaddr = 0x2, register = 0x4c */
-		tmp = ksz9031_phy_extended_read(phydev, 0x02,
-					MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
-					MII_KSZ9031_MOD_DATA_NO_POST_INC);
-		/* disable rxdll bypass (enable 2ns skew delay on RXC) */
-		tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
-		/* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
-		tmp = ksz9031_phy_extended_write(phydev, 0x02,
-					MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
-					MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);
-		/* read txc dll control - devaddr = 0x02, register = 0x4d */
-		tmp = ksz9031_phy_extended_read(phydev, 0x02,
-					MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
-					MII_KSZ9031_MOD_DATA_NO_POST_INC);
-		/* disable txdll bypass (enable 2ns skew delay on TXC) */
-		tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
-		/* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
-		tmp = ksz9031_phy_extended_write(phydev, 0x02,
-					MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
-					MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);
-		break;
-	}
-
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-	return 0;
-}
 #endif
 
 int board_init(void)